ADS131B04-Q1
ZHCSMK3B –NOVEMBER 2020 –REVISED NOVEMBER 2021
www.ti.com.cn
8.6.16 CH1_OCAL_MSB Register (Address = 0Fh) [reset = 0000h]
The CH1_OCAL_MSB register is shown in 图8-41 and described in 表8-28.
Return to the Summary Table.
图8-41. CH1_OCAL_MSB Register
15
14
13
12
11
10
9
1
8
0
OCAL1_MSB[15:8]
R/W-00000000b
7
6
5
4
3
2
OCAL1_MSB[7:0]
R/W-00000000b
表8-28. CH1_OCAL_MSB Register Field Descriptions
Bit
15:0
Field
OCAL1_MSB[15:0]
Type
Reset
Description
R/W
00000000
Channel 1 offset calibration register bits [23:8]
00000000b Value provided in two's complement format
8.6.17 CH1_OCAL_LSB Register (Address = 10h) [reset = 0000h]
The CH1_OCAL_LSB register is shown in 图8-42 and described in 表8-29.
Return to the Summary Table.
图8-42. CH1_OCAL_LSB Register
15
14
13
12
11
10
2
9
1
8
0
OCAL1_LSB[7:0]
R/W-00000000b
7
6
5
4
3
RESERVED
R-00000000b
表8-29. CH1_OCAL_LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
15:8
OCAL1_LSB[7:0]
R/W
00000000b Channel 1 offset calibration register bits [7:0]
Value provided in two's complement format
7:0
RESERVED
R
00000000b Reserved
Always reads 00000000b
Copyright © 2022 Texas Instruments Incorporated
52
Submit Document Feedback
Product Folder Links: ADS131B04-Q1
TI [ TEXAS INSTRUMENTS ]
