THCV231-Q_THCV236-Q_Rev.2.60_E
Table 37. THCV236-Q Main-Link Control Register Map
Address (Hex)
Default
(Hex)
Bit#
R/W
Name
Description
Note
Sub-Link
Master
0x50
MAINMODE setting
0: V-by-One® HS Mode
1: Sync Free Mode
HFSEL setting
0: High Frequency Mode Disable
1: High Frequency Mode Enable
COL1 setting
(*1)
(*1)
7
6
RW
RW
MAINMODE
HFSEL
-
-
when MAINMODE =0
0: Color Space Converter Disable
1: Color Space Converter Enable
when MAINMODE =1
Data Width Setting. See Table 16.
COL0 setting
5
4
RW
RW
0
COL1
COL0
-
-
(*1)
Data Width Setting. See Table 16.
3
2:1
RW
RW
0
0x0
Reserved
Reserved
-
-
TTLDRV setting
0
7:6
5
RW
R
0
0x0
0
TTLDRV
0: Weak Drive Strength
1: Normal Drive Strength
Reserved
SSEN setting
0: SSCG Disable
-
-
0x51
RW
SSEN
1: SSCG Enable
(*2)
SSCG modulation depth setting
Spread depth = ±SPREAD x 0.1% (Center Spread)
Reserved
SSCG Modulation Frequency Setting
Reserved
4:0
RW
0x05
SPREAD
FMOD
0x52
0x53
7:4
3:0
7:2
1
R
RW
R
0x0
0xD
0x00
0
-
-
-
-
RW
Reserved
Main-Link / Sub-Link Field BET Mode select
0: Main-Link Field BET Mode
1: Sub-Link Field BET Mode
Reserved
0
RW
0
BET_SEL
-
0x54
7
6:0
R
RW
0
-
-
0x3E
Reserved. Must be default setting.
0x55
-0x6C
0x6D
7:0
7:3
RW
R
0x0
Reserved
-
-
0x00
Reserved
Permanent Clock Output Enable setting
0: Permanent Clock Output Disable
1: Permanent Clock Output Enable
Permanent Clock Frequency setting
2
RW
0
OUTSEL_ENABLE
OUTSEL_SETTING
-
00: 80MHz (Clock Period : tOSC
)
(*3)
1:0
RW
0x1
01: 40MHz (Clock Period : tOSC/2)
10: 20MHz (Clock Period : tOSC/4)
11: 10MHz (Clock Period : tOSC/8)
Reserved
0x6E
7:1
0
7:0
7:2
1
R
RW
R
R
RW
0x00
1
0x00
0x00
0
-
-
-
-
-
Reserved. Must be 1
Reserved
0x6F
0x70
Reserved
Reserved. Must be 0
SSCG PLL setting register Enable
1: Enable
0
RW
0
PLL_SET_EN
-
0: Disable
0x71
-0x75
0x76
7:0
R
0x00
Reserved
-
7:6
5:0
7:4
3:0
7:0
R
RW
R
RW
RW
0x0
0x00
0x0
0x0
0xXX
Reserved
SSCG PLL setting
-
(*4)
-
PLL_SET0
PLL_SET1
0x77
Reserved
Reserved. Must be default setting.
SSCG PLL setting
-
(*4)
0x78
0x79
-0x7B
0x7C
7:0
R
0x00
Reserved. Must be default setting.
-
7:6
5:0
R
RW
0x0
0xXX
Reserved
-
(*4)
PLL_SET2
SSCG PLL setting
0x7D
-0x7F
7:0
R
0xXX
Reserved. Must be default setting.
-
*1
*2
*3
*4
Default value depends on RXDEFSEL setting when Power on sequence. RXDEFSEL=1 → default value is 0 , RXDEFSEL=0 → default value is 1.
SSEN=1 and SPREAD=0 setting is forbidden
Described value is typical value. It has variation in the range from min spec value to max spec value of tOSC
.
See Table 8, Table 17
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