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THCV231-Q 参数 Datasheet PDF下载

THCV231-Q图片预览
型号: THCV231-Q
PDF下载: 下载PDF文件 查看货源
内容描述: [SerDes transmitter and receiver with bi-directional transceiver]
分类和应用:
文件页数/大小: 58 页 / 1447 K
品牌: THINE [ THINE ELECTRONICS, INC. ]
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THCV231-Q_THCV236-Q_Rev.2.60_E  
Table 35. THCV231-Q Main-Link Control Register Map  
Address (Hex)  
Sub-Link Slave  
Default  
(Hex)  
Bit#  
R/W  
Name  
Description  
Note  
0xD0  
MAINMODE setting  
0: Forbidden  
1: Sync Free Mode  
7
RW  
1
1
MAINMODE  
-
HFSEL setting  
6
RW  
HFSEL  
0: High Frequency Mode Disable  
1: High Frequency Mode Enable  
COL1 setting  
Data Width Setting. See Table 16.  
COL0 setting  
-
5
4
RW  
RW  
0
1
COL1  
COL0  
-
-
Data Width Setting. See Table 16.  
PRE setting  
3
RW  
RW  
0
PRE  
0: Pre-Emphasis Disable  
1: Pre-Emphasis Enable  
CMLDRV setting  
00: 400mV diff p-p  
01: 600mV diff p-p  
(*1)  
2:1  
0x2  
CMLDRV  
10: 800mV diff p-p  
11: Reserved (Forbidden)  
0
7:6  
RW  
R
0
0x0  
Reserved  
Reserved  
-
-
0xD1  
SSEN setting  
5
RW  
0
SSEN  
0: SSCG Disable  
1: SSCG Enable  
(*2)  
SSCG modulation depth setting  
Spread depth = ±SPREAD x 0.1% (Center Spread)  
Reserved  
SSCG Modulation Frequency Setting  
Reserved  
4:0  
RW  
0x05  
SPREAD  
FMOD  
0xD2  
0xD3  
7:4  
3:0  
7:2  
R
RW  
R
0x0  
0xD  
0x00  
-
-
-
Field BET Mode Enable setting  
0: Normal Mode  
1
0
RW  
RW  
0
0
BET  
-
-
1: Field BET Operation  
Main-Link / Sub-Link Field BET Mode select  
0: Main-Link Field BET Mode  
1: Sub-Link Field BET Mode  
Reserved  
BET_SEL  
0xD4  
7
R
RW  
RW  
R
RW  
R
RW  
R
R
0
-
-
-
-
-
-
-
-
-
-
6:0  
7:0  
7:3  
2:0  
7:1  
0
7:0  
7:2  
1
0x3E  
0x00  
0x00  
0x1  
0x00  
1
0x00  
0x00  
0
Reserved. Must be default setting.  
Reserved  
0xD5-0xEC  
0xED  
Reserved  
Reserved  
Reserved  
0xEE  
Reserved. Must be 1  
Reserved  
0xEF  
0xF0  
Reserved  
RW  
Reserved. Must be 0  
SSCG PLL setting register Enable  
1: Enable  
0
RW  
0
PLL_SET_EN  
-
0: Disable  
0xF1  
-0xF5  
0xF6  
7:0  
R
0x00  
Reserved  
-
7:6  
5:0  
7:4  
3:0  
7:0  
7:0  
7:6  
5:0  
7:0  
R
RW  
R
RW  
RW  
RW  
R
RW  
RW  
0x0  
0xXX  
0x0  
Reserved  
SSCG PLL setting  
-
(*3)  
-
-
(*3)  
-
PLL_SET0  
PLL_SET1  
PLL_SET2  
0xF7  
Reserved  
0x0  
Reserved. Must be default setting.  
SSCG PLL setting  
0xF8  
0xF9-0xFB  
0xFC  
0xXX  
0x00  
0x0  
0xXX  
0xXX  
Reserved. Must be default setting.  
Reserved  
-
(*3)  
-
SSCG PLL setting  
0xFD-0xFF  
Reserved. Must be default setting.  
*1  
*2  
*3  
See Table 4  
SSEN=1 and SPREAD=0 setting is forbidden  
See Table 8, Table 17  
Copyright©2017 THine Electronics, Inc.  
THine Electronics, Inc.  
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Security E  
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