THCV231-Q_THCV236-Q_Rev.2.60_E
Table 33. Sub-Link Slave Control Register
Defaul
t
(Hex)
Address
(Hex)
Not
e
Bit#
R/W
Name
Description
0x80
0x81
7:0
7:1
R
R
0x00
0x00
Reserved
Reserved
2-wire serial I/F reset
Write 1: 16 pulse SCL signal is sent to 2-wire serial slave device
connected to Sub-Link Slave.
-
-
0
RW
0
2WIRE_RST
-
This bit is a remedy against SDA=L, 2-wire serial stuck condition.
Automatically cleared into 0 after reset action.0 is always read.
Reserved
Cause of interrupt 2-wire serial reset done
0: Normal operation
1: 2-wire serial reset signal has all finished
Any write action: clear this bit into 0
Cause of interrupt 2-wire serial Slave NACK
0: No NACK from remote side 2-wire serial slave ever
1: NACK from remote side 2-wire serial slave once come
Any write action: clear this bit into 0
Cause of interrupt Sub-Link Slave GPIO
0: No change in Slave GPIO inputs ever
1: Slave GPIO inputs have once changed.
This bit is cleared when GPIOn_INPUT_MONITOR (n=4,3) register
(0xC1) is read.
Cause of interrupt Sub-Link communication Error
0: No communication error on Sub-Link ever
1: Communication error on Sub-Link once happened
Any write action: clear this bit into 0
7:6
5
R
0x0
0
RW
2WIRE_RST_END_INT
2WIRE_NACK_INT
-
-
4
3
2
RW
R
0
0
0
GPIO_INT
-
0x82
RW
COMERR_INT
-
-
Cause of interrupt 2-wire serial time out
0: 2-wire serial access in time ever
1: 2-wire serial access has once had time out
Any write action: clear this bit into 0
Cause of interrupt Sub-Link time out0: Sub-Link access in time ever
1: Sub-Link has once had time out
1
0
RW
RW
0
0
2WIRE_TIMEOUT_INT
SLINK_TIMEOUT_INT
-
-
Any write action: clear this bit into 0
7:6
5
R
0x0
0
Reserved
2WIRE_RST_ENABLED_INT_ENABL
E
0: "2WIRE_RST_END_INT" is blocked to be reported to Master Side.
1: "2WIRE_RST_END_INT" is allowed to be reported to Master Side.
0: "2WIRE_NACK_INT" is blocked to be reported to Master Side.
1: "2WIRE_NACK_INT" is allowed to be reported to Master Side.
0: "GPIO_INT" is blocked to be reported to Master Side.
1: "GPIO_INT" is allowed to be reported to Master Side.
0: "COMERR_INT" is blocked to be reported to Master Side.
1: "COMERR_INT" is allowed to be reported to Master Side.
0: "2WIRE_TIMEOUT_INT" is blocked to be reported to Master Side.
1: "2WIRE_TIMEOUT_INT" is allowed to be reported to Master Side.
0: "SLINK_TIMEOUT_INT" is blocked to be reported to Master Side.
1: "SLINK_TIMEOUT_INT" is allowed to be reported to Master Side.
RW
4
3
2
1
0
RW
RW
RW
RW
RW
0
0
0
0
0
2WIRE_NACK_INT_ENABLE
GPIO_INT_ENABLE
0x83
(*1)
COMERR_INT_ENABLE
2WIRE_TIMEOUT_INT_ENABLE
SLINK_TIMEOUT_INT_ENABLE
0x84
-0x8B
7:0
7
R
R
0x00
0
Reserved
-
-
Reserved
SCL High width [tHIGH] setting. Output SCL High width is defined as
below.
((SCL_W_H + 1) * 8 + 8) * tOSC
0x8C
0x8D
6:0
7
RW
R
0x2D
0
SCL_W_H
SCL_W_L
-
-
-
Reserved
SCL Low width [tLOW] setting. Output SCL Low width is defined as
below.
6:0
RW
0x37
((SCL_W_L + 1) * 8 + 8) * tOSC
7:2
1:0
7:2
1:0
R
RW
R
0x00
0x0
0x00
0x1
Reserved
Reserved. Must be 0
Reserved
-
-
-
-
0x8E
0x8F
RW
Reserved
0x90
-0xBF
*1
7:0
R
0x00
Reserved
-
Interrupt signal from Sub-Link Slave is reported to Sub-Link Master as Cause of interrupt Sub-Link Slave Side (0x02 bit4 SLAVESIDE_INT).
Copyright©2017 THine Electronics, Inc.
THine Electronics, Inc.
34/58
Security E
THINE [ THINE ELECTRONICS, INC. ]
