THCV231-Q_THCV236-Q_Rev.2.60_E
Table 32. Sub-Link Master Control Register
Address
(Hex)
Default
(Hex)
Bit#
R/W
Register Name
Description
Note
0x00
7:3
R
0x00
0
Reserved
Interrupt condition
0: Steady state
-
2
1
R
R
INT
-
-
1: Interrupt occurred(INT output =L)
V-by-One® HS lock status
1
LOCKN
HTPDN
0: Locked (LOCKN=L)
1: Unlocked
V-by-One® HS plug status
0
7:1
0
R
R
1
0x00
0
0: Connected (HTPDN=L)
1: Not connected or Rx inactive
Reserved
Sub-Link soft reset
-
-
-
0x01
0x02
RW
SFTRST
Write 1: Sub-Link reset
Automatically cleared into 0 after reset action. 0 is always read.
Cause of interrupt access completion to register of Sub-Link Slave or
Remote side 2-wire serial Slave device
0: Access incomplete
7
RW
0
2WIRE_ACS_END_INT
1: Access complete
Any write action: clear this bit into 0
Cause of interrupt LOCKN
0: No change on lock status ever
1: Lock status has once changed
Any write action: clear this bit into 0
Cause of interrupt HTPDN
0: No change on plug status ever
1: Plug status has once changed
6
5
RW
RW
0
0
LOCKN_INT
HTPDN_INT
Any write action: clear this bit into 0
Cause of interrupt Sub-Link Slave side
0: No interrupt at Sub-Link Slave ever
1: Interrupted at Sub-Link Slave once
This bit is cleared when cause of interrupt register at Sub-Link Slave
(0x82) is cleared.
Cause of interrupt Sub-Link Master GPIO
0: No change in Master GPIO inputs ever
1: Master GPIO inputs have once changed.
This bit is cleared when GPIOn_INPUT_MONITOR (n=4~0) register
(0x41) is read.
4
3
R
R
0
0
SLAVESIDE_INT
GPIO_INT
(*1)
Cause of interrupt Sub-Link communication Error
0: No communication error on Sub-Link ever
1: Communication error on Sub-Link once happened
Any write action: clear this bit into 0
Cause of interrupt 2-wire serial time out
0: 2-wire serial access in time ever
1: 2-wire serial access has once had time out
Any write action: clear this bit into 0
Cause of interrupt Sub-Link time out
2
1
0
RW
RW
RW
0
0
0
COMERR_INT
2WIRE_TIMEOUT_INT
SLINK_TIMEOUT_INT
0: Sub-Link access in time ever
1: Sub-Link has once had time out
Any write action: clear this bit into 0
0x03
0: "2WIRE_ACS_END_INT" is blocked to take interrupt action
1: "2WIRE_ACS_END_INT" is allowed to take action on INT output
0: "LOCKN_INT" is blocked to take interrupt action
1: "LOCKN_INT" is allowed to take action on INT output
0: "HTPDN_INT" is blocked to take interrupt action
1: "HTPDN_INT" is allowed to take action on INT output
0: "SLAVESIDE_INT" is blocked to take interrupt action
1: "SLAVESIDE_INT" is allowed to take action on INT output
0: "GPIO_INT" is blocked to take interrupt action
1: "GPIO_INT" is allowed to take action on INT output
0: "COMERR_INT" is blocked to take interrupt action
1: "COMERR_INT" is allowed to take action on INT output
0: "2WIRE_TIMEOUT_INT" is blocked to take interrupt action
1: "2WIRE_TIMEOUT_INT" is allowed to take action on INT output
0: "SLINK_TIMEOUT_INT" is blocked to take interrupt action
1: "SLINK_TIMEOUT_INT" is allowed to take action on INT output
7
6
5
4
3
2
1
0
R
(*2)
0
2WIRE_ACS_END_INT_ENABLE
LOCKN_INT_ENABLE
-
-
-
-
-
-
-
-
RW
RW
RW
RW
RW
RW
RW
0
HTPDN_INT_ENABLE
0
SLAVESIDE_INT_ENABLE
GPIO_INT_ENABLE
0
0
COMERR_INT_ENABLE
2WIRE_TIMEOUT_INT_ENABLE
SLINK_TIMEOUT_INT_ENABLE
0
0
*1
*2
These registers are always active independent of Interrupt permission register.
When No clock stretching mode, the value is 1 fixed, otherwise 0 fixed
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