DS_8430_001
78Q8430 Data Sheet
6.10.2 MAC Receive Block
The receive block receives frames from the PHY via the MII interface. It strips the preamble and SOF
and passes the remainder of the received frame data and error information to the MAC receive FIFO.
The MAC receiver passes all frames received, including error frames and collisions. Dropping of error
frames is handled by the receive producer in the QUE logic.
6.10.3 MAC Control Register
The MAC Control Register (MCR) provides controls for network operation, including:
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Enable and disable transmit and receive circuit, including requests to halt at end of current packet.
Enable and disable full duplex operation and loopback modes.
Enable and disable various MAC features like excessive-deferral detection, SQE and CRC checking.
6.10.4 Transmitting a Frame
To transmit a frame, the transmit enable bit in the MCR must be set and the transmit halt request bit must
be clear. The MAC does not signal the DMA engine to transfer bytes to the MAC transmit FIFO. The
QUE transmit controller controls the transfer of bytes to the MAC transmit FIFO.
The MAC transmit block then starts transmitting the data in the FIFO, but will retain the first 64 bytes until
it has acquired the net. At that time, the MAC transmit block will request more data and transmit it until
the QUE transmit controller signals the end of the frame to be transmitted. The MAC transmit block
generates pad bytes, if needed, appends the calculated CRC to the end of the packet if requested and
transmission stops. It sets the completion bit in the Transmit Packet Status Register (TPSR), signaling
the end of a transmission, which may in turn cause an interrupt. If the QUE transmit controller indicates
an error then the MAC transmit block will transmit an MII error status and abort the frame.
The MAC transmit block does not begin transmission until the number of bytes indicated by the preload
field of the PCWR are in the MAC transmit FIFO. This is to give the IP header checksum generator a
head start in generating the checksum. This may be needed since the checksum is in the middle of the
IP header but cannot be known until the entire header is summed. The results are undefined if the
header checksum is inserted into the frame after the checksum has already been transmitted.
6.10.5 IEEE 802.3 Transmit Protocols
6.10.5.1 Interpacket Gap Timing
In half duplex mode, the gap state machine is responsible for counting the 96 bit times from the de-
assertion of the carrier sense signal, which is the inter-record gap. It breaks the 96 bit times for
inter-record gap into the first 64 bits and the last 32 bits, in order to precisely control the appropriate times
for beginning transmission. If there is any traffic within the first 64-bit times, it resets the counter and
resumes counting from zero. If there is any traffic within the last 32 bits, it continues counting and signals
the end at 96 bit times. In full duplex mode, the gap state machine starts counting at the end of
transmission and signals the end at 96 bit times (12 byte times).
6.10.5.2 Collision Processing and Back-off
If the main transmit state machine detects a collision, it starts the back-off state machine counters and
waits for the end of the back-off slot, before retransmitting the collision causing packet again. Each
back-off slot is a multiple (including zero) of 512 bit times. Each time there is a collision for the same
packet, the back-off state machine increments an internal attempt counter. A pseudo-random number
generator outputs a random number by selecting a subset of the value of the generator. The subset
grows by one bit for each subsequent attempt. This implements the equation:
0 < r < 2 k, k = min. (n, 10)
where r is the number of slot times that the MAC has to wait in case of a collision, and n is the number of
attempts. For example, after the first collision, n is 1 and r is a random number between 0 and 1. The
pseudo-random-number generator in this case is one-bit wide and gives a random number of either 0 or
Rev. 1.2
45
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
