78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION (continued)
ADDRESS 0-1: INTERRUPT CONTROL REGISTER
This register selects the events that would cause the respective interrupt pin (INTRx) for each of the ports to be
activated. User may set as many bits as required.
DFLT
BIT
NAME
TYPE
DESCRIPTION
Interrupt Pin Polarity Selection:
VALUE
7
INPOL
R/W
0
0 : Interrupt output is active-low
1 : Interrupt output is active-high
6:3
2
RSVD
JAER
R/O
R/W
--
0
Reserved
Jitter Attenuator Error Event:
When set, JAT FIFO overflow or underflow (as indicated by the FERR bit)
will cause an interrupt to be flagged.
Receiver Error Event:
When set, loss of receive signal (as indicated by the LOS bit) will cause
an interrupt to be flagged.
1
0
RXER
TXER
R/W
R/W
1
1
Transmitter Error Event:
When set, transmitter fault (as indicated by the TXNW bit) will cause an
interrupt to be flagged.
Page 9 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
