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78P2343JAT-IGT/F 参数 Datasheet PDF下载

78P2343JAT-IGT/F图片预览
型号: 78P2343JAT-IGT/F
PDF下载: 下载PDF文件 查看货源
内容描述: [PCM Transceiver, 1-Func, PQFP100, LEAD FREE, LQFP-100]
分类和应用: 电信集成电路PC
文件页数/大小: 37 页 / 351 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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78P2343JAT  
3-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
REGISTER DESCRIPTION (continued)  
LEGEND  
TYPE DESCRIPTION  
TYPE DESCRIPTION  
R/W Read or Write  
R/O  
Read only  
GLOBAL REGISTERS  
ADDRESS 0-0: MASTER CONTROL REGISTER  
DFLT  
BIT  
NAME  
TYPE  
DESCRIPTION  
VALUE  
Register Control Enable:  
0 : Pin selection overrides register settings  
7
REGEN  
R/W  
0
1 : Device is controlled via register set.  
NOTE: Pin 15 (ENDECB) must be tied low when REGEN is enabled.  
Line Speed Selection:  
Selects the line speed of all channels as well as the input clock frequency  
at the CKREF pin.  
6
5
DS3  
E3  
R/W  
R/W  
X
X
[DS3 E3] = 00 : STS-1 (51.840MHz)  
01 : E3 (34.368MHz)  
10 : DS3 (44.736MHz)  
11 : STS-1 (51.840MHz)  
NOTE: The default values of these register bits depend on the state of  
the MSL0 pin upon power-up or reset.  
Encoder/Decoder Disable:  
0 : selects NRZ digital data interface  
4
3
ENDECB  
RCLKP  
R/W  
R/W  
0
0
1 : selects AMI digital data interface  
NOTE: Relevant only when the REGEN bit is set. Otherwise, ENDECB  
pin selection prevails.  
RCLK Polarity Selection:  
0 : Receive Data clocked out on the falling-edge of RCLK  
1 : Receive Data clocked out on the rising-edge of RCLK  
TCLK Polarity Selection:  
2
1
TCLKP  
RSVD  
R/W  
R/O  
0
0 : Transmit Data clocked in on the rising-edge of TCLK  
1 : Transmit Data clocked in on the falling-edge of TCLK  
--  
Reserved  
Register Soft-Reset:  
When this bit is set, all registers are reset to their default values. Also  
resets Jitter Attenuator to “centered” states. This register bit is self-  
clearing.  
0
SRST  
R/W  
0
Page 8 of 37  
2005 Teridian Semiconductor Corporation  
Rev 2.2  
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