78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION (continued)
ADDRESS N-1: STATUS MONITOR REGISTER
DFLT
BIT
NAME
TYPE
DESCRIPTION
VALUE
Jitter Attenuator FIFO Error Flag:
This bit is set whenever a FIFO overflow or underflow occurred. It is
reset after a read operation to this register.
7
6:4
3
FERR
RSVD
LOS
R/O
R/O
R/O
X
0 : Proper Operation
1 : FIFO Overflow/Underflow
X
X
Reserved
Loss-of-Signal Indication:
0 : Signal Detector detecting a valid receive input signal
1 : Standards-based Loss-of-Signal indication
NOTE: RPOSx and RNEGx are forced low when LOS=’1’. RCLK will
continue to output a line rate clock
Transmitter Not-Working Indication:
0 : Transmitter OK
2
1
0
TXNW
RSVD
SGLO
R/O
R/O
R/O
X
X
X
1 : Transmitter not working
Reserved
Signal Low Indication:
0 : Receive signal level OK
1 : Receive signal level too low / Loss of signal
Page 11 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
