78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION
REGISTER ADDRESSING
Address Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Sub-Address
SA[1]
Bit 1
Bit 0
Read/
Write
Port Address
Assignment
PA[3]
PA[2]
PA[1]
PA[0]
SA[2]
SA[0]
R/W*
REGISTER TABLE
a) PA[3:0] = 0 : Global Registers
Reg.
Name
Sub
Addr
Description
Master Control
Interrupt Control
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REGEN
<0>
INPOL
<0>
E3
<X>
ENDECB RCLKP
TCLKP
<0>
JAER
<0>
SRST
<0>
TXER
<1>
MSCR
(R/W)
DS3
<X>
0
1
--
<0>
--
<0>
--
INTC
(R/W)
RXER
<1>
--
--
2
3
4
5
6
7
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
--
<0>
--
--
<0>
--
--
<0>
--
--
<0>
--
--
<0>
--
--
<0>
--
--
<0>
--
--
<0>
--
--
--
--
--
--
--
--
--
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
b) PA[3:0] = 1-3 : Port-Specific Registers
Reg.
Name
Sub
Addr
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MDCR
(R/W)
PDTX
<0>
PDRX
<0>
LBO
<1>
LLBKA
<0>
LLBKB
<0>
RLBK
<0>
MON
<0>
TXEN
<1>
0
Mode Control
STAT
(R/O)
--
--
--
1
2
3
Status Monitor
Reserved
FERR
LOS
TXNW
--
SGLO
RSVD
<1>
<1>
<0>
<1>
<0>
<0>
<1>
<0>
<0>
<0>
JACR
(R/W)
Jitter Attenuator
Control
JAEN
<X>
JASL
<X>
JLBK
<0>
ESP[1]
<1>
ESP[0]
<1>
JABW
<X>
4
5
6
7
RSVD
RSVD
RSVD
RSVD
Reserved
Reserved
Reserved
Reserved
--
--
--
--
--
--
--
--
--
--
<0>
--
<0>
--
<0>
--
<0>
--
<0>
--
<0>
--
--
--
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
Note: Shaded registers in Register Table are reserved for Teridian internal use only. Accessing reserved or
undefined registers may cause undesirable operation.
Page 7 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
