78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION
(continued)
ADDRESS 0-1: INTERRUPT CONTROL REGISTER
This register selects the events that would cause the
LOS
pin to be activated. User may set as many bits as
required.
BIT
7
6:4
3
2
NAME
INPOL
RSVD
JAFLG
JAER
TYPE
R/W
R/O
R/W
R/W
DFLT
VALUE
0
X
0
0
DESCRIPTION
Interrupt Pin Polarity Selection:
0 : Interrupt output is active-low
1 : Interrupt output is active-high
Reserved
Reserved for test only. Must be set to ‘0’.
Jitter Attenuator Error Event:
When set, JAT FIFO overflow or underflow (as indicated by the FERR bit)
will cause an interrupt to be flagged.
Receiver Error Event:
When set, loss of receive signal (as indicated by the LOS bit) will cause
an interrupt to be flagged.
Transmitter Error Event:
When set, transmitter fault (as indicated by the TXNW bit) will cause an
interrupt to be flagged.
1
RXER
R/W
1
0
TXER
R/W
0
-9-
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