78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
PIN DESCRIPTION
LEGEND
TYPE
A
CI
CIU
CID
DESCRIPTION
Analog Pin
CMOS Digital Input
CMOS Digital Input w/ Pull-up
CMOS Digital Input w/ Pull-down
TYPE DESCRIPTION
CIS
CO
COZ
S
CMOS Schmitt Trigger Input
CMOS Digital Output
CMOS Tristate Digital Output
Supply
TRANSMITTER PINS
PIN
PIN
NAME
TYPE DESCRIPTION
TQFP PLCC
Transmit Positive Data/Transmit NRZ:
When ENDEC =’1’, a logic one on this pin generates a positive AMI pulse
on the coax. This pin should not be high at the same time that
corresponding TNEG is high.
16
17
14
15
CI
CI
TPOS
TNEG
When ENDEC =’0’, data on this pin is encoded and converted into
positive and negative AMI pulses.
Transmit Negative Data:
When ENDEC bit =’1’, a logic one on this pin generates a negative AMI
pulse on the coax. This pin should not be high at the same time that
corresponding TPOS is high.
When ENDEC bit =’0’, this pin is ignored.
Transmitter Clock Input:
This clock signal is used to latch the respective TPOS and TNEG
signals into the 78P2341JAT. The frequency should correspond to the
line-rate frequency as follows:
18
16
CIS
TCLK
E3 : 34.368 MHz
DS3: 44.736 MHz
STS-1: 51.840 MHz
If CKREF pin pulled high or left floating, TCLK is also used as the
reference clock for the 78P2341JAT.
Line Out:
9
11
9
11
LOUTP
LOUTN
Differential AMI Outputs. Requires a 1:2CT center-tapped transformer
and a shunt termination resistor. See APPLICATION INFORMATION
section for more info.
A
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TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
