78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION (continued)
ADDRESS 1-3: JITTER ATTENUATOR CONTROL REGISTER
DFLT
BIT
NAME
TYPE
DESCRIPTION
VALUE
Jitter Attenuator Enable:
0 : Disables jitter attenuation function
1 : Enables jitter attenuation function
7
JAEN
R/W
X
Note: The default value of this register bit depends on the state of the
TXEN and MON pins upon power up or a reset.
Jitter Attenuation Selection:
0 : Jitter Attenuator on the receive path
1 : Jitter Attenuator on the transmit path
6
JASL
R/W
X
Note: The default value of this register bit depends on the state of the
TXEN and MON pins upon power up or a reset.
Jitter Attenuator Local Loopback Enable:
0 : Normal Operation
1 : TCLKx, TPOSx, TNEGx connected to JAT input and RCLKx, RPOSx,
5
4
JLBK
R/W
R/W
0
0
RNEGx connected to JAT output
Note: If both RLBK and JLBK bits are set, RLBK mode takes priority.
Reserved. Must be set to zero.
RSVD
FIFO Elastic Store Pointer Selection:
00 : Pass-through
ESP
[1:0]
3:2
1
R/W
R/W
11
0
01 : 8 UI
10 : 16 UI
11 : 32 UI
RSVD
Reserved. Must be set to zero.
Jitter Attenuator Bandwidth Selection:
0 : Low bandwidth
1 : High bandwidth
(see JAT Bandwidth Selection Table on page 5)
0
JABW
R/W
X
Note that the default value of this register bit depends on the power-up
state of the MSL0 pin. If the state of the MSL0 pin selects E3 or DS3
mode, the default value of JABW is ‘0’. If the state of the MSL0 pin
selects STS1 mode, the default value of JABW is ‘1’.
- 12 -
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
