78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION (continued)
ADDRESS 1-1: STATUS MONITOR REGISTER
DFLT
BIT
NAME
TYPE
DESCRIPTION
VALUE
Jitter Attenuator FIFO Error Flag: This bit is set whenever a FIFO
overflow or underflow occurred. It is reset after a read operation to this
register.
0 : Proper Operation
1 : FIFO Overflow/Underflow
7
FERR
R/O
R/O
X
X
6:4 JAF[2:0]
Jitter Attenuator Monitor Flags: Used for internal test only. Ignore during
normal operation.
Loss-of-Signal Indication:
0 : Signal Detector detecting a valid receive input signal
1 : Standards-based Loss-of-Signal indication
3
LOS
R/O
X
Note: RPOSx and RNEGx are forced low when LOS=’1’ ; RCLK will
continue to output a line rate clock
Transmitter Not-Working Indication:
0 : Transmitter OK
1 : Transmitter not working
2
1
0
TXNW
SGHI
R/O
R/O
R/O
X
X
X
Signal High Indication: Used for internal test only. Ignore during normal
operation
Signal Low Indication:
0 : Receive signal level OK
SGLO
1 : Receive signal level too low / Loss of signal
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