78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION (continued)
SPECIFIC REGISTERS
For PA[3:0] = 1 only. Accessing a register with port address greater than 1 constitutes an invalid command, and
the read/write operation will be ignored.
ADDRESS 1-0: MODE CONTROL REGISTER
DFLT
BIT
NAME
TYPE
DESCRIPTION
VALUE
Transmitter Power-Down:
0 : Normal Operation
1 : Power-Down
7
PDTX
R/W
0
Receiver Power-Down:
0 : Normal Operation
1 : Power-Down
6
PDRX
R/W
0
Transmitter Line Build-Out (DS3 and STS-1 only):
0 : ≥ 225ft of cable attached to the cross-connect
1 : < 225ft of cable attached to the cross-connect
(Note this bit is inactive when REGEN bit is ‘0’ )
5
4
3
LBO
RSVD
LLBK
R/W
R/W
R/W
1
0
0
Reserved
Local (Analog) Loopback Mode Enable:
0 : Normal operation
1 : Loops LOUTP and LOUTN back onto LINP and LINN
(Note this bit is inactive when REGEN bit is ‘0’ )
Remote (Digital) Loopback Enable:
0 : Normal Operation
1 : Loops RCLK, RPOS, and RNEG back onto TCLK, TPOS, and TNEG
(Note this bit is inactive when REGEN bit is ‘0’ )
2
1
0
RLBK
MON
TXEN
R/W
R/W
R/W
0
0
1
Monitor Mode Enable: Used for reception of split-off signals that are flat-
attenuated by at least 16dB but no more than 20dB.
0 : Disable
1 : Enable
(Note this bit is inactive when REGEN bit is ‘0’ )
Transmitter Output Enable:
0 : Transmit driver is disabled
1 : Normal Operation
(Note this bit is inactive when REGEN bit is ‘0’ )
- 10 -
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
