DS_8010C_024
73S8010C Data Sheet
SDA
SCL
MSB
LSB
MSB
LSB
9
1-7
8
9
1-8
START
condition
STOP
ACK bit
ACK bit
ADDRESS bits
R/W bit
DATA bits
condition
Figure 3: I2C Bus Read Protocol
Conditions
2.3 I2C-bus Timing
Symbol
Fsclk
Parameter
Clock frequency
Clock low
Min.
Typ.
Max. UNIT
400
kHz
µs
µs
µs
ns
ns
µs
µs
Tlow
1.3
0.6
0.6
100
5
Thi
Clock high
Thdsta
Tsudat
Thddat
Tsusto
Tbuf
Hold time START condition
Data set up time
Data hold time
900
Set up time STOP condition
0.6
1.3
Bus free time between a STOP and
START condition
SDA
SCL
Tbuf
Tlow
Thi
Thdsta
Tsudat
Thddat
Tsusto
Figure 4: I2C Bus Timing Diagram
Rev. 1.5
9
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
