DS_8010C_024
73S8010C Data Sheet
5 Voltage Supervision
Two voltage supervisors constantly check the level of the VDD and VCC voltages. A card deactivation
sequence is forced when a fault occurs for any of these voltage supervisors.
The digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage
range to interface with the system controller. The VDD voltage supervisor is also used to initialize the
ISO-7816-3 sequencer at power-on, and to deactivate the card at power-off or when a fault occurs. The
voltage threshold of the VDD voltage supervisor is internally set by default to 2.3 V nominal. However, it
may be desirable in some applications, to modify this threshold value. The pin VDDF_ADJ (pin 18 in the
SO package, pin 17 in the QFN package) is used to connect an external resistor REXT1 to ground to raise
the VDD fault voltage to another value, VDDF (refer to Figure 11). The resistor value is defined as follows:
REXT = 180 kΩ / (VDDF - 2.33)
An alternative (more accurate) method of adjusting the VDD fault voltage is to use a resistive network of
R3 from the pin to supply and R4 from the pin to ground (see Figure 11). In order to set the new
threshold voltage, the equivalent resistance must be determined. This resistance value will be
designated Kx. Kx is defined as R4/(R4+R5). Kx is calculated as:
Kx = (2.649 / VTH) - 0.6042 where VTH is the desired new threshold voltage.
To determine the values of R4 and R5, use the following formulas.
R5 = 72000 / Kx
R4 = R5*(Kx / (1 – Kx))
Taking the example above, where a VDD fault threshold voltage of 2.7 V is desired, solving for Kx gives:
Kx = (2.649 / 2.7) - 0.6042 = 0.377.
Solving for R5 gives:
Solving for R4 gives:
R5 = 72000 / 0.377 = 191 kΩ.
R4 = 191000 *(0.377 / (1 – 0.377)) = 115.6 kΩ.
Using standard 1% resistor values gives R5 = 191 kΩ and R4 = 115 kΩ. These values give an equivalent
resistance of Kx = 0.376, a 0.3% error.
If the 2.3 V default threshold is used, the VDDF_ADJ pin must be left unconnected.
6 Power Down
A power down function is provided via the PWRDN pin (active high). When activated, the Power Down
(PD) mode disables all the internal analog functions, including the card analog interface, the oscillators
and the DC-DC converter, to put the 73S8010C in its lowest power consumption mode. PD mode is only
allowed in the deactivated condition (out of a card session, when the Start/Stop bit is set to 0 from the I2C
host controller).
The host controller invokes the power down state when it is desirable to save power. The signal PRES
remains functional in PD mode such that a card insertion sets INT high. The micro-controller must then
set PWRDN low and wait for the internal stabilization time prior to starting any card session (prior to
setting the Start/Stop bit to 1).
Resumption of the normal mode occurs approximately 10 ms (stabilization of the internal oscillators +
reset of the circuitry) after PWRDN is set low. No card activation should be invoked during this 10 ms
time period. If a card is present, INT can be used as an indication that the circuit has completed its
recovery from power down state. INT will go high at the end of the stabilization period. Should the
Start/Stop be set to 1 during PWRDN = 1, or within the 10 ms internal stabilization / reset time, it will not
be taken into account and the card interface will remain inactive. Since Start/Stop is taken into account
on its edges, it should be toggled low and high again after the 10 ms to activate a card.
Figure 5 illustrates the sequencing of the PD and Normal modes. PWRDN must be connected to GND if
the power down function is not used.
Rev. 1.5
11
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
