73S8010C Data Sheet
DS_8010C_024
1.4 Microcontroller Interface
PIN
(SO) (QFN)
PIN
Name
Description
INT
23
8
22
5
Interrupt output (negative assertion): Interrupt output signal to the
processor. A 20 kΩ pull up to VDD is provided internally.
PWRDN
Power Down control input: Active High. When Power Down (PD) mode is
activated, all internal analog functions are disabled to place the 73S8010C
in its lowest power consumption mode. Must be tied to ground when the
power down function is not used.
SAD0
SAD1
SAD2
1
2
3
29
30
31
Serial device address bits: Digital inputs for address selection that allow
the connection of up to 8 devices in parallel. Address selections as follows:
SAD2
SAD1
SAD0
I2C Address (7 bits)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0x40
0x42
0x44
0x46
0x48
0x4A
0x4C
0x4E
Pins SAD0 and SAD1 are internally pulled-down and SAD2 is
internally pulled-up.
The default address when left unconnected is 48h.
I2C clock signal input.
I2C bi-directional serial data signal.
SCL
19
20
26
18
19
26
SDA
I/OUC
System controller data I/O to/from the card. Includes internal pull-up
resistor to VDD.
AUX1UC
AUX2UC
27
28
27
28
System controller auxiliary data I/O to/from the card. Includes internal pull-
up resistor to VDD.
System controller auxiliary data I/O to/from the card. Includes internal pull-
up resistor to VDD.
6
Rev. 1.5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
