DS_8010C_024
73S8010C Data Sheet
2 Host Interface (I2C Bus)
A fast-mode 400 kHz I2C bus slave interface is used for controlling the device and reading the status of
the device via the data pin SDA and clock pin SCL. The bus has 3 address select pins, SAD0, SAD1,
and SAD2. This allows up to 8 devices to be connected in parallel.
Table 1: Device Address Selections
SAD2
SAD1
SAD0
I2C Address (7 bits)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0x40
0x42
0x44
0x46
0x48
0x4A
0x4C
0x4E
Bit 0 of the I2C address is the R/W bit. Refer to Figure 2 and Figure 3 for usage.
2.1 Host Interface Control
Table 2 describes the Host Interface Control Register bits (power-on Reset = 0x00).
Table 2: Host Control Register
Name
Bit Description
Start/Stop
0
When set, initiates an activation and a cold reset procedure; when reset, initiates
a deactivation sequence.
Warm reset
1
When set, initiates a warm reset procedure; automatically reset by hardware
when the card starts answering or when the card is declared mute.
5 V and 3 V
Clock Stop
2
3
4
When set, VCC = 3 V; when reset, VCC = 5 V.
When set, card clock is stopped. Bit 4 determines the card clock stop level.
When set, card clock stops high; when reset card clock stops low.
Clock Stop
Level
Clksel1
Clksel2
5
Bits 5 and 6 determine the clock rate to the card according to the following table.
CLKDIV1
CLKDIV2
Clock Rate
XTALIN/8
XTALIN/4
XTALIN/2
XTALIN
0
0
1
1
0
1
1
0
6
I/O enable
7
When set, data is transferred between I/O (AUX1, AUX2) and I/OUC (AUX1UC,
AUX2UC); when reset, I/O (AUX1, AUX2) and I/OUC (AUX1UC, AUX2UC) are
high impedance.
I2C-bus Write to the Control Register
The I2C-bus Write command to the control register follows the format shown in Figure 2.
After the START condition, the master sends a slave address. This address is seven bits long followed
by an eighth bit, which is an opcode bit (R/W) – a ‘zero’ indicates the master will write data to the control
register. After the R/W bit, the ’zero’ ACK bit is sent to the master by the device. The master now starts
sending the 8 bits of data to the control register during the DATA bits time. After the DATA bits, the ‘zero’
Rev. 1.5
7
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
