73S8010C Data Sheet
DS_8010C_024
PRES
INT
OFF follows PRES regardless of PWRDN
PWRDN during a card
session has no effect
PWRDN has effect when
the cardi s deactivated
PWRDN
Internal RC OSC
Start/Stop bit
~10ms
After setting PWRDN = 0,
the controller must wait at
least 10ms before setting
Start/Stop = 1
EMV / ISO deactivation
time ~= 100 uS
Figure 5: Power Down Mode Operation
7 Over-temperature Monitor
A built-in detector monitors die temperature. When an over-temperature condition occurs (most likely
resulting from a heavily loaded card interface, including short circuits), a card deactivation sequence is
initiated, and a fault condition is reported to the system controller (bit 4 of the status register is set and
generates an interrupt).
8 Activation Sequence
After Power on Reset, the INT signal is low until VDD is stable. When VDD has been stable for
approximately 10 ms and the INT signal is high, the system controller may read the status register to see
if the card is present. If all the status bits are satisfactory, the system controller can initiate the activation
sequence by writing a ‘1’ to the Start/Stop bit (bit 0 of the Control register).
The following steps and Figure 6 show the activation sequence and the timing of the card control signals
when the system controller initiates the Start/Stop bit (bit 0) of the control register:
1. Voltage VCC to the card should be valid by the end of t1. If VCC is not valid for any reason, then the
session is aborted.
2. Turn I/O to reception mode at the end of t1.
3. CLK is applied to the card at the end of t2.
4. RST (to the card) is set high at the end of t3.
Start/Stop
VCC
IO
CLK
RST
t1
t2
t3
t1 = 0.510 ms (timing by 1.5 MHz internal Oscillator), I/O in reception mode
t2 ≥ 0.5 μs, CLK starts
t3 ≥ 42000 card clock cycles, RST set high
Figure 6: Activation Sequence
12
Rev. 1.5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
