DS_8009CN_026
73S8009CN Data Sheet
See NOTE 1
0.1F
VDD
VPC
See NOTE 5
0.1F
C2
0.1F
C1
10µF
C4
See NOTE 4
C3
10µH
VDD_monitor_to_uC
ON/OFF_Control_from_uC
USB D- to/from_uC
USB D+ to/from_uC
OFF_interrupt_to_uC
I/OUC_to/from_uC
AUX1UC_to/from_uC
AUX2UC_to/from_uC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
ON/OFF
DM
I/OUC
AUX1UC
AUX2UC
CMDVCC%
CMDVCC#
RSTIN
I/O
47K
AUX1
AUX2
VCC
RST
CMDVCC%_from_uC
CMDVCC#_from_uC
47K
CLKIN
RDY
10K
27pF
C5
GND
RSTIN_from_uC
CLKIN_from_uC
RDY_status_to_uC
See
NOTE 3
0
See NOTE 7
See
NOTE 2
73S80009CN
32 QFN
0
27pF
C6
See
NOTE 3
VDD
47K
R2
20K
SC/USB_from_uC
See NOTE 6
NOTES:
1) VPC = 2.7V to 6.5V DC
2) Resistor footprint is included in case some filtering is needed on CLK
0.47µF,
Low ESR (<100mohms)
should be placed near the
SC connecter contact
4.7µF
C2
Card detection
switch is
normally closed
C7
3) Capacitors C5 and C6 are provisional and their footprints should be added for added noise rejection
if necessary.
4) Inductor must be rated for 400 mA maximum peak current.
5) VDD - 3.3V, +/- 0.3V, 40mA max. Schematic assumes VDD is monitored by the host controller.
Requires min two 0.1µF caps to gnd)
6) Resistors are necessary to provide isolation between powered host and "OFF" 73S8009CN. Signals
should be driven low in this condition.
CLK track should be routed
far from RST, I/O, C4 and C8
7) The RDY signal is optional. A short delay before releasing RSTIN should suffice for the RDY
signal function.
Smart Card Connector
Figure 4: Typical 73S8009CN Application Schematic without a Main System Switch
Rev. 1.4
15
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
