73S8009CN Data Sheet
DS_8009_026
See NOTE 1
0.1F
VDD
VPC
See NOTE 5
0.1F
C2
0.1F
C1
10µF
C4
See NOTE 4
C3
10µH
VDD_supply_to_uC
USB D- to/from_uC
USB D+ to/from_uC
OFF_interrupt_to_uC
I/OUC_to/from_uC
Pushbutton Switch
SW1
AUX1UC_to/from_uC
AUX2UC_to/from_uC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
ON/OFF
DM
I/OUC
AUX1UC
AUX2UC
CMDVCC%
CMDVCC#
RSTIN
I/O
AUX1
AUX2
VCC
RST
CMDVCC%_from_uC
CMDVCC#_from_uC
CLKIN
RDY
27pF
GND
RSTIN_from_uC
CLKIN_from_uC
RDY_status_to_uC
See
NOTE 3
C5
See NOTE 6
See
73S80009CN
32 QFN
NOTE 2
OFF_ACK_from_uC
OFF_REQ_to_uC
0
27pF
C6
See
NOTE 3
VDD
R2
20K
SC/USB_from_uC
0.47µF,
Low ESR (<100mohms)
should be placed near the
SC connecter contact
4.7µF
C7
Card detection
switch is
normally closed
C8
NOTES:
1) VPC = 2.7V to 6.5V DC
2) Resistor footprint is included in case some filtering is needed on CLK
3) Capacitors C4 and C5 are provisional and their footprints should be added for added noise rejection
if necessary.
CLK track should be routed
far from RST, I/O, C4 and C8
4) Inductor must be rated for 400 mA maximum peak current.
5) VDD - 3.3V, +/- 0.3V, 40mA max. Schematic assumes VDD supplies power to the host controller.
Requires min two 0.1µF caps to gnd)
6) The RDY signal is optional. A short delay before releasing RSTIN should suffice for the RDY
signal function.
Smart Card Connector
Figure 3: Typical 73S8009CN Application Schematic with a Main System Switch
14
Rev. 1.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
