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73S8009CN 参数 Datasheet PDF下载

73S8009CN图片预览
型号: 73S8009CN
PDF下载: 下载PDF文件 查看货源
内容描述: 二合一ISO- 7816和USB通用智能卡接口IC [Combo ISO-7816 and USB Universal Smart Card Interface IC]
分类和应用:
文件页数/大小: 30 页 / 342 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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DS_8009CN_026  
73S8009CN Data Sheet  
3.6 Activation and De-activation Sequence  
The host controller is fully responsible for the activation sequencing of the smart card signals CLK, RST,  
I/O, AUX1 and AUX2. All these signals are held low by the 73S8009CN when the card is in the de-  
activated state. Upon card activation (the fall of CMDVCC (#/%)), all the signals are held low by the  
73S8009CN until RDY goes high. The host should set the signals RSTIN, I/OUC, CLKIN, AUX1UC and  
AUX2UC low prior to activating the card and allow RDY to go high before transitioning any of these  
signals. In order to initiate activation, the card must be present and OFF must be high.  
At t1 (500us), if RDY=0 or overcurrent, circuit will de-activate (safety feature)  
t1  
CMDVCC5 or CMDVCC3  
VCC  
I/OUC  
I/O  
VCC valid  
Ignored  
I/O = I/OUC if RDY=1  
RDY  
Ignored  
Ignored  
RSTIN  
RST  
RST = RSTIN if RDY=1  
CLKIN  
CLK  
CLK=CLKIN if RDY=1  
I/O, AUX1, AUX2, CLK, RST are held LOW until RDY = 1 and CMDVCCx = 0  
Figure 5: Activation Sequence  
Deactivation is initiated either by the system controller by setting both CMDVCC (#/%) high, or  
automatically in the event of hardware faults or assertion of the OFF_ACK signal. Hardware faults are  
over-current, under-voltage, and card extraction during the session. The host can manage the I/O  
signals, CLKIN, RSTIN, and CMDVCC (#/%) to create other de-activation sequences for non-emergency  
situations.  
The following steps show the deactivation sequence and the timing of the card control signals when the  
system controller sets the CMDVCC(x)B high:  
1. RST goes low at the end of time t1.  
2. De-assert CLK at the end of time t2.  
3. I/O goes low at the end of time t3. Exit reception mode.  
4. De-assert internal VCC_ON at the end of time t4. After a delay, VCC is de-asserted.  
Note: Since the 73S8009CN does not control the waveshape of CLK (it is determined by the input form  
the host CLKIN), there is no guarantee that the duty cycle of the last CLK high pulse will conform to duty  
cycle requirements during an emergency deactivation.  
Rev. 1.4  
19  
 
 
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