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73S1217F-IMR/F 参数 Datasheet PDF下载

73S1217F-IMR/F图片预览
型号: 73S1217F-IMR/F
PDF下载: 下载PDF文件 查看货源
内容描述: 总线供电80515的系统级芯片, USB , ISO 7816 / EMV ,密码键盘和更多 [Bus-Powered 80515 System-on-Chip with USB, ISO 7816 / EMV, PINpad and More]
分类和应用: 多功能外围设备微控制器和处理器时钟
文件页数/大小: 140 页 / 1066 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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73S1217F Data Sheet  
DS_1217F_002  
Table 26: Control Bits for External Interrupts  
Enable Bit Description  
Flag Bit  
IE0  
Description  
External interrupt 0 flag  
EX0  
EX1  
EX2  
EX3  
EX4  
EX5  
EX6  
Enable external interrupt 0  
Enable external interrupt 1  
Enable external interrupt 2  
Enable external interrupt 3  
Enable external interrupt 4  
Enable external interrupt 5  
Enable external interrupt 6  
IE1  
External interrupt 1 flag  
External interrupt 2 flag  
External interrupt 3 flag  
External interrupt 4 flag  
External interrupt 5 flag  
External interrupt 6 flag  
IEX2  
IEX3  
IEX4  
IEX5  
IEX6  
1.7.5.4  
Power Down Interrupt Logic  
The 73S1217F contains special interrupt logic to allow INT0 to wake up the CPU from a power down  
(CPU STOP) state. See the Power Control Modes section for details.  
1.7.5.5  
Interrupt Priority Level Structure  
All interrupt sources are combined in groups, as shown in Table 27.  
Table 27: Priority Level Groups  
Group  
0
1
2
3
4
5
External interrupt 0  
Timer 0 interrupt  
External interrupt 1  
Timer 1 interrupt  
Serial channel 0 interrupt  
Serial channel 1 interrupt  
External interrupt 2  
External interrupt 3  
External interrupt 4  
External interrupt 5  
External interrupt 6  
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or  
clearing one bit in the special function register IP0 and one in IP1. If requests of the same priority level  
are received simultaneously, an internal polling sequence as per Table 31 determines which request is  
serviced first.  
IEN enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its  
own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler.  
Interrupt Priority 0 Register (IP0): 0xA9 Å 0x00  
Table 28: The IP0 Register  
MSB  
LSB  
IP0.0  
WDTS  
IP0.5  
IP0.4  
IP0.3  
IP0.2  
IP0.1  
Note: WDTS is not used for interrupt controls.  
40  
Rev. 1.2  
 
 
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