DS_1217F_002
73S1217F Data Sheet
Interrupt Request Register (IRCON): 0xC0 Å 0x00
Table 24: The IRCON Register
MSB
LSB
–
–
–
EX6
IEX5
IEX4
IEX3
IEX2
Bit
Symbol
–
Function
IRCON.7
IRCON.6
IRCON.5
IRCON.4
IRCON.3
IRCON.2
IRCON.1
IRCON.0
–
IEX6
IEX5
IEX4
IEX3
IEX2
–
External interrupt 6 flag.
External interrupt 5 flag.
External interrupt 4 flag.
External interrupt 3 flag.
External interrupt 2 flag.
1.7.5.3
External Interrupts
The external interrupts (external to the CPU core) are connected as shown in Table 25. Interrupts with
multiple sources are OR’ed together and individual interrupt source control is provided in XRAM SFRs to
mask the individual interrupt sources and provide the corresponding interrupt flags. Multifunction USR
[7:0] pins control Interrupts 0 and 1. Dedicated external interrupt pins INT2 and INT3 control interrupts 2
and 3. The polarity of interrupts 2 and 3 is programmable in the MPU. Interrupts 4, 5 and 6 have multiple
peripheral sources and are multiplexed to one of these three interrupts. The peripheral functions will be
described in subsequent sections. Generic 80515 MPU literature states that interrupts 4 through 6 are
defined as rising edge sensitive. Thus, the hardware signals attached to interrupts 4, 5 and 6 are
converted to rising edge level by the hardware.
SFR (special function register) enable bits must be set to permit any of these interrupts to occur.
Likewise, each interrupt has its own flag bit that is set by the interrupt hardware and is reset automatically
by the MPU interrupt handler.
Table 25: External MPU Interrupts
External
Connection
Polarity
Flag Reset
Interrupt
0
1
2
3
4
5
6
USR I/O High Priority
see USRIntCtlx
see USRIntCtlx
Edge selectable
Edge selectable
N/A
Automatic
Automatic
Automatic
Automatic
Automatic
Automatic
Automatic
USR I/O Low Priority
External Interrupt Pin INT2
External Interrupt Pin INT3
Smart Card Interrupts
USB, RTC and Keypad
I2C, VDD_Fault, Analog Comp
N/A
N/A
Note: Interrupts 4, 5 and 6 have multiple interrupt sources and the flag bits are cleared upon reading of
the corresponding register. To prevent any interrupts from being ignored, the register containing multiple
interrupt flags should be stored temporary to allow each interrupt flag to be tested separately to see which
interrupt(s) is/are pending.
Rev. 1.2
39
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