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73S1217F-IMR/F 参数 Datasheet PDF下载

73S1217F-IMR/F图片预览
型号: 73S1217F-IMR/F
PDF下载: 下载PDF文件 查看货源
内容描述: 总线供电80515的系统级芯片, USB , ISO 7816 / EMV ,密码键盘和更多 [Bus-Powered 80515 System-on-Chip with USB, ISO 7816 / EMV, PINpad and More]
分类和应用: 多功能外围设备微控制器和处理器时钟
文件页数/大小: 140 页 / 1066 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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73S1217F Data Sheet  
DS_1217F_002  
1.7.6 UART  
The 80515 core of the 73S1217F includes two separate UARTs that can be programmed to communicate  
with a host. The 73S1217F can only connect one UART at a time since there is only one set of TX and  
Rx pins. The MISCtl0 register is used to select which UART is connected to the TX and RX pins. Each  
UART has a different set of operating modes that the user can select according to their needs. The  
UART is a dedicated 2-wire serial interface, which can communicate with an external host processor at  
up to 115,200 bits/s. The TX and RX pins operate at the VDD supply voltage levels and should never  
exceed 3.6V. The operation of each pin is as follows:  
RX: Serial input data is applied at this pin. Conforming to RS-232 standard, the bytes are input LSB first.  
The voltage applied at RX must not exceed 3.6V.  
TX: This pin is used to output the serial data. The bytes are output LSB first.  
The 73S1217F has several UART-related read/write registers. All UART transfers are programmable for  
parity enable, parity select, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud  
rates from 300 to 115200 bps. Table 47 shows the selectable UART operation modes and Table 48  
shows how the baud rates are calculated.  
Table 33: UART Modes  
UART 0  
UART 1  
Start bit, 8 data bits, parity, stop bit, variable  
baud rate (internal baud rate generator)  
Mode 0  
Mode 1  
Mode 2  
Mode 3  
N/A  
Start bit, 8 data bits, stop bit, variable  
baud rate (internal baud rate generator  
or timer 1)  
Start bit, 8 data bits, stop bit, variable baud  
rate (internal baud rate generator)  
Start bit, 8 data bits, parity, stop bit,  
fixed baud rate 1/32 or 1/64 of fCKMPU  
N/A  
N/A  
Start bit, 8 data bits, parity, stop bit,  
variable baud rate (internal baud rate  
generator or timer 1)  
Note: Parity of serial data is available through the P flag of the accumulator. Seven-bit serial modes with  
parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of 8-bit  
output data. Seven-bit serial modes without parity can be simulated by setting bit 7 to a constant 1.8-bit  
serial modes with parity can be simulated by setting and reading the 9th bit, using the control bits  
S0CON3 and S1CON3 in the S0CON and S1CON SFRs.  
Table 34: Baud Rate Generation  
Using Timer 1  
2smod * fCKMPU/ (384 * (256-TH1))  
N/A  
Using Internal Baud Rate Generator  
2smod * fCKMPU/(64 * (210-S0REL))  
Serial Interface 0  
Serial Interface 1  
f
CKMPU/(32 * (210-S1REL))  
Note: S0REL (9:0) and S1REL (9:0) are 10-bit values derived by combining bits from the respective timer  
reload registers SxRELH (bits 1:0) and SxRELL (bits 7:0). TH1 is the high byte of timer 1. The SMOD bit  
is located in the PCON SFR.  
42  
Rev. 1.2  
 
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