DS_1210F_001
73S1210F Data Sheet
1.7.8 WD Timer (Software Watchdog Timer)
The software watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles.
After a reset, the watchdog timer is disabled and all registers are set to zero. The watchdog consists of a
16-bit counter (WDT), a reload register (WDTREL), prescalers (by 2 and by 16), and control logic. Once
the watchdog starts, it cannot be stopped unless the internal reset signal becomes active.
WD Timer Start Procedure: The WDT is started by setting the SWDT flag. When the WDT register
enters the state 0x7CFF, an asynchronous WDTS signal will become active. The signal WDTS sets bit 6
in the IP0 register and requests a reset state. WDTS is cleared either by the reset signal or by changing
the state of the WDT timer.
Refreshing the WD Timer: The watchdog timer must be refreshed regularly to prevent the reset request
signal from becoming active. This requirement imposes an obligation on the programmer to issue two
instructions. The first instruction sets WDT and the second instruction sets SWDT. The maximum delay
allowed between setting WDT and SWDT is 12 clock cycles. If this period has expired and SWDT has
not been set, WDT is automatically reset, otherwise the watchdog timer is reloaded with the content of
the WDTREL register and WDT is automatically reset.
Interrupt Enable 0 Register (IEN0): 0xA8 0x00
Table 43: The IEN0 Register
MSB
EAL
LSB
EX0
WDT
ET2
ES0
ET1
EX1
ET0
Bit
Symbol
Function
IEN0.7
IEN0.6
EAL
EAL = 0 – disable all interrupts.
Watchdog timer refresh flag.
WDT
Set to initiate a refresh of the watchdog timer. Must be set directly before
SWDT is set to prevent an unintentional refresh of the watchdog timer. WDT
is reset by hardware 12 clock cycles after it has been set.
IEN0.5
IEN0.4
IEN0.3
IEN0.2
IEN0.1
IEN0.0
–
ES0
ET1
EX1
ET0
EX0
ES0 = 0 – disable serial channel 0 interrupt.
ET1 = 0 – disable timer 1 overflow interrupt.
EX1 = 0 – disable external interrupt 1.
ET0 = 0 – disable timer 0 overflow interrupt.
EX0 = 0 – disable external interrupt 0.
Rev. 1.4
47
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