73S1210F Data Sheet
DS_1210F_001
1.7.6.2
Serial Interface 1
The Serial Interface 1 can operate in 2 modes:
•
Mode A
This mode is similar to Mode 2 and 3 of Serial interface 0, 11 bits are transmitted or received: a start bit
(0), 8 data bits (LSB first), a programmable 9th bit, and a stop bit (1). The 9th bit can be used to control
the parity of the serial interface: at transmission, bit TB81 in S1CON is outputted as the 9th bit, and at
receive, the 9th bit affects RB81 in Special Function Register S1CON. The only difference between
Mode 3 and A is that in Mode A only the internal baud rate generator can be use to specify baud rate.
•
Mode B
This mode is similar to Mode 1 of Serial interface 0. Pin RX serves as input, and TX serves as serial
output. No external shift clock is used, 10 bits are transmitted: a start bit (always 0), 8 data bits (LSB
first), and a stop bit (always 1). On receive, a start bit synchronizes the transmission, 8 data bits are
available by reading S1BUF, and stop bit sets the flag RB81 in the Special Function Register
S1CON. In mode 1, the internal baud rate generator is use to specify the baud rate.
The S1BUF register is used to read/write data to/from the serial 1 interface.
Serial Interface Control Register (S1CON): 0x9B 0x00
The function of the serial port depends on the setting of the Serial Port Control Register S1CON.
Table 39: The S1CON Register
MSB
SM
LSB
RI1
–
SM21
REN1
TB81
RB81
TI1
Bit
Symbol
Function
S1CON.7
SM
Sets the UART operation mode.
SM
0
Mode
Description
9-bit UART
8-bit UART
Baud Rate
variable
A
B
1
variable
S1CON.6
S1CON.5
S1CON.4
S1CON.3
–
SM21
REN1
TB81
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9th transmitted data bit in Mode A. Set or cleared by the MPU, depending
on the function it performs (parity check, multiprocessor communication, etc.).
S1CON.2
S1CON.1
RB81
TI1
In Mode B, if sm21 is 0, rb81 is the stop bit. Must be cleared by software.
Transmit interrupt flag, set by hardware after completion of a serial transfer.
Must be cleared by software.
S1CON.0
RI1
Receive interrupt flag, set by hardware after completion of a serial reception.
Must be cleared by software.
Multiprocessor operation mode: The feature of receiving 9 bits in Modes 2 and 3 of Serial Interface 0 or in
Mode A of Serial Interface 1 can be used for multiprocessor communication. In this case, the slave
processors have bit SM20 in S0CON or SM21 in S1CON set to 1. When the master processor outputs
slave’s address, it sets the 9th bit to 1, causing a serial port receive interrupt in all the slaves. The slave
processors compare the received byte with their network address. If there is a match, the addressed slave
will clear SM20 or SM21 and receive the rest of the message, while other slaves will leave the SM20 or
SM21 bit unaffected and ignore this message. After addressing the slave, the host will output the rest of the
message with the 9th bit set to 0, so no serial port receive interrupt will be generated in unselected slaves.
44
Rev. 1.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
