73S1210F Data Sheet
DS_1210F_001
Mode 0
Putting either timer/counter into mode 0 configures it as an 8-bit timer/counter with a divide-by-32
prescaler. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from
all 1’s to all 0’s, it sets the timer overflow flag TF0. The overflow flag TF0 then can be used to request an
interrupt. The counted input is enabled to the timer when TRx = 1 and either GATE = 0 or TX = 1 (setting
GATE = 1 allows the timer to be controlled by external input TX, to facilitate pulse width measurements).
TRx are control bits in the special function register TCON; GATE is in TMOD. The 13-bit register consists
of all 8 bits of TH1 and the lower 5 bits of TL0. The upper 3 bits of TL0 are indeterminate and should be
ignored. Setting the run flag (TRx) does not clear the registers. Mode 0 operation is the same for timer 0
as for timer 1.
Mode 1
Mode 1 is the same as mode 0, except that the timer register is run with all 16 bits.
Mode 2
Mode 2 configures the timer register as an 8-bit counter (TLx) with automatic reload. The overflow from
TLx not only sets TFx, but also reloads TLx with the contents of THx, which is preset by software. The
reload leaves THx unchanged.
Mode 3
Mode 3 has different effects on timer 0 and timer 1. Timer 1 in mode 3 simply holds its count. The effect
is the same as setting TR1 = 0. Timer 0 in mode 3 establishes TL0 and TH0 as two separate counters.
TL0 uses the timer 0 control bits: C/T, GATE, TR0, INT0, and TF0. TH0 is locked into a timer function
(counting machine cycles) and takes over the use of TR1 and TF1 from timer 1. Thus, TH0 now controls
the "timer 1" interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer or counter. When
timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or
can still be used by the serial channel as a baud rate generator, or in fact, in any application not requiring
an interrupt from timer 1 itself.
Timer/Counter Control Register (TCON): 0x88 0x00
Table 42: The TCON Register
MSB
TF1
LSB
IT0
TR1
TF0
TR0
IE1
IT1
IE0
Bit
Symbol
Function
TCON.7
TCON.6
TCON.5
TCON.4
TF1
TR1
TF0
TR0
Timer 1 overflow flag.
Not used for interrupt control.
Timer 0 overflow flag.
Not used for interrupt control.
Interrupt 1 edge flag is set by hardware when the falling edge on external
interrupt int1 is observed. Cleared when an interrupt is processed.
TCON.3
TCON.2
TCON.1
TCON.0
IE1
IT1
IE0
IT0
Interrupt 1 type control bit. 1 selects falling edge and 0 selects low level for
input pin to cause an interrupt.
Interrupt 0 edge flag is set by hardware when the falling edge on external
interrupt int0 is observed. Cleared when an interrupt is processed.
Interrupt 0 type control bit. 1 selects falling edge and 0 sets low level for
input pin to cause interrupt.
46
Rev. 1.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
