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73S1210F-68IM/F/P 参数 Datasheet PDF下载

73S1210F-68IM/F/P图片预览
型号: 73S1210F-68IM/F/P
PDF下载: 下载PDF文件 查看货源
内容描述: 自包含智能卡读卡器与密码键盘和电源管理 [Self-Contained Smart Card Reader with PINpad and Power Management]
分类和应用: 微控制器和处理器外围集成电路uCs集成电路uPs集成电路
文件页数/大小: 126 页 / 1200 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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DS_1210F_001  
73S1210F Data Sheet  
Mode 3  
The only difference between Mode 2 and Mode 3 is that in Mode 3 either internal baud rate generator  
or timer 1 can be use to specify baud rate.  
The S0BUF register is used to read/write data to/from the serial 0 interface.  
Serial Interface 0 Control Register (S0CON): 0x9B 0x00  
Transmit and receive data are transferred via this register.  
Table 38: The S0CON Register  
MSB  
LSB  
RI0  
SM0  
SM1  
SM20  
REN0  
TB80  
RB80  
TI0  
Bit  
Symbol  
Function  
S0CON.7  
SM0  
SM1  
These two bits set the UART0 mode:  
Mode  
Description  
N/A  
SM0  
SM1  
0
1
2
3
0
0
1
1
0
1
0
1
S0CON.6  
8-bit UART  
9-bit UART  
9-bit UART  
S0CON.5  
S0CON.4  
S0CON.3  
SM20  
REN0  
TB80  
Enables the inter-processor communication feature.  
If set, enables serial reception. Cleared by software to disable reception.  
The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the MPU,  
depending on the function it performs (parity check, multiprocessor  
communication etc.).  
S0CON.2  
RB80  
In Modes 2 and 3 it is the 9th data bit received. In Mode 1, if SM20 is 0,  
RB80 is the stop bit. In Mode 0 this bit is not used. Must be cleared by  
software.  
S0CON.1  
S0CON.0  
TI0  
RI0  
Transmit interrupt flag, set by hardware after completion of a serial transfer.  
Must be cleared by software.  
Receive interrupt flag, set by hardware after completion of a serial  
reception. Must be cleared by software.  
Rev. 1.4  
43