73S1210F Data Sheet
DS_1210F_001
Interrupt Enable 1 Register (IEN1): 0xB8 0x00
Table 44: The IEN1 Register
MSB
LSB
–
SWDT
EX6
EX5
EX4
EX3
EX2
–
Bit
Symbol
Function
IEN1.7
IEN1.6
–
SWDT Watchdog timer start/refresh flag. Set to activate/refresh the watchdog timer.
When directly set after setting WDT, a watchdog timer refresh is performed. Bit
SWDT is reset by the hardware 12 clock cycles after it has been set.
IEN1.5
IEN1.4
IEN1.3
IEN1.2
IEN1.1
IEN1.0
EX6
EX5
EX4
EX3
EX2
–
EX6 = 0 – disable external interrupt 6.
EX5 = 0 – disable external interrupt 5.
EX4 = 0 – disable external interrupt 4.
EX3 = 0 – disable external interrupt 3.
EX2 = 0 – disable external interrupt 2.
Interrupt Priority 0 Register (IP0): 0xA9 0x00
Table 45: The IP0 Register
MSB
–
LSB
IP0.0
WDTS
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
Bit
Symbol
WDTS
Function
IP0.6
Watchdog timer status flag. Set when the watchdog timer has expired. The
internal reset will be generated, but this bit will not be cleared by the reset.
This allows the user program to determine if the watchdog timer caused the
reset to occur and respond accordingly. Can be read and cleared by software.
Note: The remaining bits in the IP0 register are not used for watchdog control.
Watchdog Timer Reload Register (WDTREL): 0x86 0x00
Table 46: The WDTREL Register
MSB
LSB
WDPSEL WDREL6 WDREL5 WDREL4 WDREL3 WDREL2 WDREL1 WDREL0
Bit
Symbol
Function
Prescaler select bit. When set, the watchdog is clocked through an
additional divide-by-16 prescaler.
WDTREL.7
WDPSEL
WDTREL.6
to
WDTREL.0
Seven bit reload value for the high-byte of the watchdog timer. This value is
WDREL6-0 loaded to the WDT when a refresh is triggered by a consecutive setting of
bits WDT and SWDT.
48
Rev. 1.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
