DS_1x22_017
73M1822/73M1922 Data Sheet
If the HC bit (Register 0x02[0]) is reset to 0 (default), CTL (Bit 0 of TX data) is used for the host to request a
control frame. The 16-bit serial data bit stream received on the SDIN is defined as follows:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 CTL
If the CTL bit in the TX data stream is set high by the host, a control frame will be initiated before the next
data frame. A control frame allows the host controller to read or write status and control to the 73M1x22.
If the HC bit (Register 0x02[0]) is set to 1, a control frame is initiated between every pair of data frames.
The 16-bit serial data bit stream received on the SDIN is defined as follows:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0
In both cases, Bit 15 is transmitted/received first in time. Bits RX[15:0] are the receive code word. Bits
TX[17:0] are the transmit code word.
The serial bit stream of a control frame on the SDIN pin is defined as:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W
A6 A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
The serial bit stream of a control frame on the SDOUT pin is defined as:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
If the R/W (Bit 15 of the control word) bit is set to a 0, the data byte transmitted on the SDOUT pin is all
zeros and the data received on the SDIN pin is written to the register pointed to by the received address bits
(A6-A0). If the R/W bit is set to a 1, there is no write to any register and the data byte transmitted on the
SDOUT pin is the data contained in the register pointed to by address bits A6-A0. Only one control frame
can occur between any two data frames.
8.2 Data and Control Frame Timing
Figure 18 illustrates data and control frames timing of 8 kHz sample rate.
8 KHz
SCLK
FS
SDIN
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
1
R
0
A
0
A
0
DI
DI
DI
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
0
T
X
X
A
0
I
T
X
X
SDOUT
RX
DO
DO
DO
RX
R
O
R
Data Frame
Control Frame
Data Frame
Figure 18: Data and Control Frames Timing Diagram
The position of a control data frame is controlled by the SPOS bit (Register 0x02[1]). If SPOS is zero, the
control frames occur midway between data frames, i.e., the time between data frames are equal. If SPOS
is set to 1, the control frame is ¼ of the way between consecutive data frames, i.e., the control frame is
closer to the first data frame. This is illustrated in Figure 19. The SPOS bit has no effect in Slave or Daisy
Chain mode
Rev. 1.6
47
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
