DS_1x22_017
73M1822/73M1922 Data Sheet
this happens, the system clock will transition to PLLclk without any glitches through a specially designed
de-glitch mux.
The following tables show the register values for several common clock or crystal frequencies and sample
rates. By using these tables, computing the values for the registers is not necessary in most cases.
Table 32: Clock Generation Register Settings for Fxtal = 27 MHz
Bit,
Reg Address
PRST,
ICHP,
PDVSR KVCO_H
PSEQ
0x08
NDVSR NSEQ NRST
Ichp KVCO
Fs (kHz)
0x09
0xEF
0xEF
0xEF
0xEF
0xEF
0xE9
0x0A
0x20
0x31
0x32
0x24
0x46
0x17
0x0B
0x13
0x15
0x19
0x20
0x26
0x19
0x0C
0x10
0x04
0x1A
XX
0x0D
0x04
0x02
0x04
0x00
0x04
0x04
(μA)
(2:0)
7.2
8.0
0xDA
0xDA
0xDA
0xDA
0xDA
0xA4
8
0
1
2
4
6
7
10
10
8
9.6
12.0
14.4
16.0
0x14
0x1A
12
6
Table 33: Clock Generation Register Settings for Fxtal = 24.576 MHz
Bit,
Reg Address
PRST,
ICHP,
PSEQ PDVSR KVCO_H NDVSR NSEQ NRST
Ichp KVCO
Fs (kHz)
0x08
XX
XX
XX
XX
XX
XX
0x09
0x0A
0x0A
0x0A
0x0A
0x0A
0x08
0x0A
0x10
0x11
0x22
0x14
0x26
0x17
0x0B
0x0D
0x0F
0x12
0x16
0x1B
0x18
0x0C
0x02
XX
0x0D
0x01
0x00
0x00
0x01
0x00
0x00
(μA)
(2:0)
7.2
8.0
6
6
8
6
8
6
0
1
2
4
6
7
9.6
XX
12.0
0x02
XX
14.4
16.0
XX
Table 34: Clock Generation Register Settings for Fxtal = 9.216 MHz
Bit,
Reg Address
PRST,
ICHP,
PSEQ PDVSR KVCO_H NDVSR NSEQ NRST
Ichp KVCO
Fs (kHz)
7.2
0x08
XX
XX
XX
XX
XX
XX
0x09
0x04
0x04
0x04
0x04
0x08
0x03
0x0A
0x20
0x31
0x32
0x24
0x66
0x17
0x0B
0x0E
0x10
0x13
0x18
0x39
0x18
0x0C
0x14
XX
0x0D
0x04
0x00
0x04
0x00
0x04
0xC0
(μA)
(2:0)
8
0
1
2
4
6
7
8.0
10
10
8
9.6
0x10
XX
12.0
14.4
16.0
0x1A
XX
16
6
Rev. 1.6
43
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