DS_1x22_017
73M1822/73M1922 Data Sheet
7.5 PLL System Timing Control
Table 48 describes the registers used for PLL system timing control.
Table 37: PLL System Timing Controls
Function
Mnemonic
Register
Location
Type
Description
PSEQ
PRST
0x08[7:0]
0x09[7:5]
0x09[4:0]
0x0A[7:4]
0x0A[2:0]
W
W
W
W
W
Sequence of the divisor. If PRST=0, this register is ignored.
Rate at which the sequence register is reset.
Divisor value. Default is 01111.
PDVSR
ICHP
The sizes of the charge pump current in the PLL.
KVCOH
The magnitude of KVCO associated with the VCO within PLL.
The following table shows proper KVCOH values per each
desired PLL VOC frequency.
KVCOH2 KVCOH1 KVCOH0 Fvco
Kvco
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
33 MHz 38 MHz/V
36 MHz 38 MHz/V
44 MHz 40 MHz/V
48 MHz 40 MHz/V
57 MHz 63 MHz/V
61 MHz 63 MHz/V
69 MHz 69 MHz/V
73 MHz 69 MHz/V
NDVSR
NSEQ
0x0B[6:0]
0x0C[7:0]
0x0D[7]
W
W
R
Divisor value. If NRST=0, this register is ignored.
Divisor sequence.
LOKDET
Phase Locked Loop Lock Detect
0 = PLL is not locked. (Default)
1 = PLL is locked to PCLK.
CHNGFS
0x0D[3]
W
Sample Rate Change Sequence Enable
0 = No Fs change sequence generated. (Default)
1 = Fs change sequence is enabled.
Setting this bit to 1 minimizes the barrier power loss period
during the sample rate changes. This bit is recommended to
be set to 1 for the applications requiring dynamic sample rate
changes such as V.34 and V.90 modems, etc.
NRST
0x0D[2:0]
W
Represents the rate at which the NCO sequence register is
reset.
Rev. 1.6
45
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
