73M1822/73M1922 Data Sheet
DS_1x22_017
8 MAFE Serial Interface
The serial data port is a bi-directional port that is supported by most host processors. This is a simple four-
wire interface consisting of a clock, frame sync, data in and data out. The typical I2S (Inter-IC Sound, NXP
semiconductor) bus can be easily converted into a MAFE-compatible interface. Although the 73M1x22 is a
peripheral to the host processor, the device can be either a master or slave to the host. The M/S pin
dictates what is in control of the serial port. If the M/S pin is a logic 1 (default), the device is the master; if a
logic 0, then it is a slave.
The 73M1x22 chip set can be configured to use one of two framing modes. The active low frame
synchronization (FS) signal is pin configurable by the TYPE pin. When the TYPE pin is unconnected or
pulled up to logic “1” (mode 1), an early FS is generated in the bit clock prior to the first data bit transmitted
or received. When this pin is pulled down to ground (mode 0), a late FS operates as a chip select; the FS
signal is active for all bits that are transmitted or received. The TYPE input is sampled during the device
reset and is ignored at all other times. The final state of the TYPE pin as the TEST! pin is de-asserted
determines the frame synchronization mode used. In master mode, FS is an output and generated by the
MicroDAA at the frame sync (or sample) rate, Fs. In daisy chain/slave mode, regardless of the type, the
master device will only support early mode. The slave device can be of either an early or late type. For
every data Fs, 16 bits are transmitted and 16 bits are received.
The standard 73M1822 device supports the late frame sync mode only. If a need for a frame sync
early mode is required, contact the Teridian Marketing department for details.
8.1 Data and Control Frame Formats
The serial bit stream of a data frame from the SDOUT pin are defined as follows:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RX2
RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 RX7 RX6 RX5 RX4 RX3
RX1 RX0
Figure 17 shows data and control frames with early and late frame synch.
SCLK
FS(late)
FS(early)
TX15
TX14
TX13
RX13
TX12
RX12
TX11
RX11
TX10
RX10
TX9
RX9
TX8
RX8
TX7
RX7
TX6
RX6
TX5
RX5
TX4
RX4
TX3
RX3
TX2
RX2
TX1
RX1
SDIN
CTL/TX0
RX15 RX14
RX0
SDOUT
Data Frame With Early/Late Frame Sync
SCLK
FS(late)
FS(early)
R/W
zero
A6
A5
A4
A3
A2
A1
A0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SDIN
SDOUT
zero
zero
zero
zero
zero
zero
zero
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Control Frame With Early/Late Frame Sync
Figure 17: Serial Port Timing Diagram
46
Rev. 1.6
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
