73M1822/73M1922 Data Sheet
Table 35: Clock Generation Register Settings for Fxtal = 24.000 MHz
DS_1x22_017
Bit,
Reg Address
PRST, ICHP,
PDVSR KVCO_H
PSEQ
0x08
NDVSR NSEQ NRST
Ichp KVCO
Fs (kHz)
0x09
0xEF
0x2C
0xEF
0x66
0xCA
0xE9
0x0A
0x30
0x31
0x42
0x14
0x46
0x17
0x0B
0x0C
0x1A
0x10
0x1E
0x14
0x3E
0x1E
0x0D
0x04
0x04
0x04
0x04
0x05
0xC4
(μA)
10
10
12
6
(2:0)
7.2
8.0
0xDA
0x02
0xDA
0x08
0x54
0xA4
0x 5
0
1
2
4
6
7
0x13
0x1C
0x0E
0x1C
0x1C
9.6
12
14.4
16.0
12
6
Table 36: Clock Generation Register Settings for Fxtal = 25.35 MHz
Bit,
Reg Address
PRST, ICHP,
PSEQ PDVSR KVCO_H NDVSR NSEQ NRST
Ichp
(μA)
KVCO
(2:0)
Fs(kHz)
0x08
0x92
0x40
0x09
0xF4
0xCA
0x0A
0x50
0x17
0x0B
0x1A
0x1D
0x0C
0x06
0x02
0x0D
7.2
16
0x02
14
6
0
7
0xC1
44
Rev. 1.6
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
