Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
To adjust the clock rate using the digital rate adjust, the appropriate values must be written to PREG[16:0]
and QREG[1:0]. The default frequency is 32,768 RTCLK cycles per second. To shift the clock frequency
by ∆ ppm, calculate PREG[16:0] and QREG[1:0] using the following equation:
32768⋅8
1+ ∆ ⋅10−6
4⋅ PREG + QREG = floor
+ 0.5
For example, for a shift of -988 ppm, 4⋅PREG + QREG = 262403 = 0x40103. PREG[16:0] = 0x10040 and
QREG[1:0] = 0x03. The default values of PREG[16:0] and QREG[1:0], corresponding to zero adjustment,
are 0x10000 and 0x0, respectively.
The RTC timing may be observed on the TMUXOUT pin by setting TMUX[4:0] to 0x10 or 0x11.
Default values for RTCA_ADJ, PREG[16:0] and QREG[1:0] should be nominal values, at the center of
the adjustment range. Extreme values (zero for example) can cause incorrect operation.
If the crystal temperature coefficient is known, the MPU can integrate temperature and correct the RTC
time as necessary.
The sub-second register of the RTC, SUBSEC, can be read by the MPU after the one second interrupt and
before reaching the next one second boundary. SUBSEC contains the count remaining, in 1/256 second
nominal clock periods, until the next one second boundary. When the RST_SUBSEC bit is written, the
SUBSEC counter is restarted. Reading and resetting the sub-second counter can be used as part of an
algorithm to accurately set the RTC.
When setting the RTC_SEC register, it is important to take into account that the associated write operation
will be performed only in the next second boundary.
1.5.4 Temperature Sensor
The device includes an on-chip temperature sensor for determining the temperature of the bandgap
reference. If automatic temperature measurement is not performed by selecting CHOP_E[1:0] = 00, the
MPU may request an alternate multiplexer frame containing the temperature sensor output by asserting
MUX_ALT. The primary use of the temperature data is to determine the magnitude of compensation
required to offset the thermal drift in the system (see Section 3.4 Temperature Compensation).
1.5.5 Physical Memory
Flash Memory
The 71M6531D and 71M6532D include 128 KB of on-chip flash memory. The 71M6531F and 71M6532F
offer 256 KB of flash memory. The flash memory primarily contains MPU and CE program code. It also
contains images of the CE and MPU data in RAM, as well as of I/O RAM. On power-up, before enabling
the CE, the MPU copies these images to their respective locations.
The flash memory is segmented into individually erasable pages that contain 1024 bytes.
Flash space allocated for the CE program is limited to 4096 16-bit words (8 KB). The CE program must
begin on a 1-KB boundary of the flash address space. The CE_LCTN[7:0] word defines which 1-KB
boundary contains the CE code. Thus, the first CE instruction is located at 1024*CE_LCTN[7:0].
Flash Write Procedures
The MPU may write to the flash memory. This is one of the non-volatile storage options available to the
user in addition to external EEPROM.
FLSH_PWE (flash program write enable) differentiates 80515 data store instructions (MOVX@DPTR,A)
between Flash and XRAM write operations. This bit must be cleared by the MPU after each byte write
operation. Write operations to this bit are inhibited when interrupts are enabled.
The MPU cannot write to flash while the CE is executing its code from flash. Two interrupts warn of collisions
between the MPU firmware and the CE timing. If a flash write operation is attempted while the CE is
busy, the flash write will not execute and the FWCOL0 interrupt will be issued. If a flash write is still in
progress when the CE would otherwise begin a code pass, the code pass is skipped, the write operation
is completed, and the FWCOL1 interrupt is issued.
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