FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Register
(Alternate Name)
SFR
Address
Bit Field
Name
R/W
Description
This register is used to initiate either the Flash
Mass Erase cycle or the Flash Page Erase cycle.
See the Flash Memory section for details.
ERASE
(FLSH_ERASE)
0x94
W
FL_BANK
0xB6[2:0]
R/W Flash Bank Selection.
Flash Page Erase Address register. Contains
the flash memory page address (page 0 through
page 127) that will be erased during the Page
Erase cycle (default = 0x00).
PGADDR
(FLSH_PGADR[5:0])
0xB7
R/W
Must be re-written for each new Page Erase
cycle.
Program Write Enable:
0: MOVX commands refer to XRAM
0xB2[0]
FLSH_PWE
R/W
W
Space, normal operation (default).
1: MOVX @DPTR,A moves A to Program
Space (Flash) @ DPTR.
Mass Erase Enable:
0: Mass Erase disabled (default).
1: Mass Erase enabled.
Must be re-written for each new Mass Erase
cycle.
Enables security provisions that prevent external
reading of flash memory and CE program RAM.
This bit is reset on chip reset and may only be
set. Attempts to write zero are ignored.
0xB2[1]
0xB2[6]
FLSH_MEEN
SECURE
FLSHCRL
R/W
R
0xB2[7]
0xE8[0]
PREBOOT
IE_XFER
Indicates that the preboot sequence is active.
This flag monitors the XFER_BUSY interrupt.
R/W It is set by hardware and must be cleared by
the interrupt handler.
This flag monitors the RTC_1SEC interrupt. It
R/W is set by the hardware and must be cleared by
the interrupt handler.
0xE8[1]
0xE8[2]
0xE8[3]
IE_RTC
This flag indicates that a flash write was in
progress while the CE was busy.
FWCOL1
FWCOL0
R/W
This flag indicates that a flash write was
R/W attempted when the CE was attempting to
begin a code pass.
IFLAGS
This flag indicates that the wake-up pushbutton
was pressed.
This flag indicates that the MPU was awakened
by the autowake timer.
PLL_RISE Interrupt Flag:
Write 0 to clear the PLL_RISE interrupt flag.
PLL_FALL Interrupt Flag:
Write 0 to clear the PLL_FALL interrupt flag.
0xE8[4]
0xE8[5]
0xE8[6]
0xE8[7]
IE_PB
R/W
IE_WAKE
PLL_RISE
PLL_FALL
R/W
R/W
R/W
Interrupt inputs. The MPU may read these bits
to see the status of external interrupts INT0 up
to INT6. These bits do not have any memory
and are primarily intended for debug use.
The WDT is reset when a 1 is written to this
bit.
0xF8[6:0] INT6 … INT0
0xF8[7]
WD_RST
R
INTBITS
(INT0 … INT6)
W
Only byte operations on the entire INTBITS register should be used when
writing. The byte must have all bits set except the bits that are to be
cleared.
v1.3
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