Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
1.4.5 Instruction Set
All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set
and of the associated op-codes is contained in the 71M653X Software User’s Guide (SUG).
1.4.6 UARTs
The 71M6531D/F and 71M6532D/F include a UART (UART0) that can be programmed to communicate
with a variety of AMR modules. A second UART (UART1) is connected to the optical port, as described
in Section 1.5.6 Optical Interface.
The UARTs are dedicated 2-wire serial interfaces, which can communicate with an external host processor
at up to 38,400 bits/s (with MPU clock = 1.2288 MHz). The operation of the RX and TX UART0 pins is as
follows:
•
•
UART0 RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are
input LSB first.
UART0 TX: This pin is used to output the serial data. The bytes are output LSB first.
The 71M6531D/F and 71M6532D/F have several UART-related registers for the control and buffering of
serial data.
A single SFR register serves as both the transmit buffer and receive buffer (S0BUF, SFR 0x99 for UART0
and S1BUF, SFR 0x9C for UART1). When written by the MPU, S0BUF and S1BUF act as transmit buffers for
their respective channels, and when read by the MPU, they act as receive buffers. Writing data to the
transmit buffer starts the transmission by the associated UART. Received data are available by reading
from the receive buffer. Both UARTs can simultaneously transmit and receive data.
WDCON[7] (SFR 0xD8) selects whether timer 1 or the internal baud rate generator is used. All UART
transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable
communication baud rates from 300 to 38400 bps. Table 15 shows how the baud rates are calculated.
Table 16 shows the selectable UART operation modes.
Table 15: Baud Rate Generation
Using Timer 1
(WDCON[7] = 0)
Using Internal Baud Rate Generator
(WDCON[7] = 1)
2smod * fCKMPU/ (384 * (256-TH1))
2smod * fCKMPU/(64 * (210-S0REL))
UART0
UART1
N/A
fCKMPU/(32 * (210-S1REL))
S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload registers
(S0RELL, S0RELH, S1RELL, S1RELH). SMOD is the SMOD bit in the SFR PCON register. TH1 is the high
byte of timer 1.
Table 16: UART Modes
UART 0
UART 1
Start bit, 8 data bits, parity, stop bit, variable
baud rate (internal baud rate generator)
Mode 0
Mode 1
Mode 2
Mode 3
N/A
Start bit, 8 data bits, stop bit, variable
baud rate (internal baud rate generator
or timer 1)
Start bit, 8 data bits, parity, stop bit,
fixed baud rate 1/32 or 1/64 of fCKMPU
Start bit, 8 data bits, parity, stop bit, va-
riable baud rate (internal baud rate ge-
nerator or timer 1)
Start bit, 8 data bits, stop bit, variable baud
rate (internal baud rate generator)
N/A
N/A
Parity of serial data is available through the P flag of the accumulator. 7-bit serial modes with
parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of
8-bit output data. 7-bit serial modes without parity can be simulated by setting bit 7 to a constant 1.
8-bit serial modes with parity can be simulated by setting and reading the 9th bit, using the control
bits TB80 (S0CON[3]) and TB81 (S1CON[3]) in the S0CON (SFR 0x98) and S1CON (SFR 0x9B) SFRs
for transmit and RB81 (S1CON[2]) for receive operations.
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