欢迎访问ic37.com |
会员登录 免费注册
发布采购

71M6531D_10 参数 Datasheet PDF下载

71M6531D_10图片预览
型号: 71M6531D_10
PDF下载: 下载PDF文件 查看货源
内容描述: 电能计量IC [Energy Meter IC]
分类和应用:
文件页数/大小: 120 页 / 1966 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
 浏览型号71M6531D_10的Datasheet PDF文件第24页浏览型号71M6531D_10的Datasheet PDF文件第25页浏览型号71M6531D_10的Datasheet PDF文件第26页浏览型号71M6531D_10的Datasheet PDF文件第27页浏览型号71M6531D_10的Datasheet PDF文件第29页浏览型号71M6531D_10的Datasheet PDF文件第30页浏览型号71M6531D_10的Datasheet PDF文件第31页浏览型号71M6531D_10的Datasheet PDF文件第32页  
Data Sheet 71M6531D/F-71M6532D/F  
FDS 6531/6532 005  
Bit  
Symbol  
RB81  
Function  
In Modes A and B, it is the 9th data bit received. In Mode B, if SM21 is 0,  
RB81 is the stop bit. Must be cleared by software  
S1CON[2]  
Transmit interrupt flag, set by hardware after completion of a serial transfer.  
Must be cleared by software.  
S1CON[1]  
S1CON[0]  
TI1  
RI1  
Receive interrupt flag, set by hardware after completion of a serial reception.  
Must be cleared by software.  
Table 19: PCON Register Bit Description (SFR 0x87)  
Bit  
Symbol  
Function  
The SMOD bit doubles the baud rate when set  
Not used.  
PCON[7]  
PCON[6:2]  
SMOD  
Stops MPU flash access and MPU peripherals including timers and  
UARTs when set until an external interrupt is received.  
PCON[1]  
PCON[0]  
STOP  
IDLE  
Stops MPU flash access when set until an internal interrupt is received.  
1.4.7 Timers and Counters  
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured  
for counter or timer operations.  
In timer mode, the register is incremented every 12 MPU clock cycles. In counter mode, the register is  
incremented when the falling edge is observed at the corresponding input signal T0 or T1 (T0 and T1 are  
the timer gating inputs derived from certain DIO pins, see Section 1.5.7 Digital I/O). Since it takes 2 machine  
cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the clock frequency (CKMPU).  
There are no restrictions on the duty cycle, however to ensure proper recognition of the 0 or 1 state, an  
input should be stable for at least 1 machine cycle.  
Four operating modes can be selected for Timer 0 and Timer 1, as shown in Table 20 and Table 21. The  
TMOD Register, shown in Table 22, is used to select the appropriate mode. The timer/counter operation  
is controlled by the TCON Register, which is shown in Table 23. Bits TR1 (TCON[6]) and TR0 (TCON[4]) in  
the TCON register start their associated timers when set.  
Table 20: Timers/Counters Mode Description  
M1  
0
M0  
0
Mode  
Function  
13-bit Counter/Timer mode with 5 lower bits in the TL0 or TL1 register  
Mode 0 and the remaining 8 bits in the TH0 or TH1 register (for Timer 0 and Timer  
1, respectively). The 3 high order bits of TL0 and TL1 are held at zero.  
0
1
Mode 1 16-bit Counter/Timer mode.  
8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or  
TH1, while TL0 or TL1 is incremented every machine cycle. When TL(x)  
overflows, a value from TH(x) is copied to TL(x) (where x = 0 for  
counter/timer 0 or 1 for counter/timer 1.  
1
1
0
1
Mode 2  
If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops.  
If Timer 0 M1 and M0 bits are set to 1, Timer 0 acts as two independent  
Mode 3  
8-bit Timer/Counters.  
In Mode 3, TL0 is affected by TR0 and gate control bits and sets the TF0 flag on overflow, while TH0  
is affected by the TR1 bit and the TF1 flag is set on overflow.  
Table 21 specifies the combinations of operation modes allowed for Timer 0 and Timer 1.  
28  
© 2005-2010 TERIDIAN Semiconductor Corporation  
v1.3  
 
 
 
 复制成功!