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71M6531D_10 参数 Datasheet PDF下载

71M6531D_10图片预览
型号: 71M6531D_10
PDF下载: 下载PDF文件 查看货源
内容描述: 电能计量IC [Energy Meter IC]
分类和应用:
文件页数/大小: 120 页 / 1966 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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FDS 6531/6532 005  
Data Sheet 71M6531D/F-71M6532D/F  
Accumulator (ACC, A, SFR 0xE0):  
ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The  
mnemonics for accumulator-specific instructions refer to accumulator as A, not ACC.  
B Register (SFR 0xF0):  
The B register is used during multiply and divide instructions. It can also be used as a scratch-pad register  
to hold temporary data.  
Program Status Word (PSW, SFR 0xD0):  
This register contains various flags and control bits for the selection of the register banks (see Table 11).  
Table 11: PSW Bit Functions (SFR 0xD0)  
PSW Bit  
Symbol  
CV  
Function  
7
6
Carry flag.  
AC  
Auxiliary Carry flag for BCD operations.  
General-purpose Flag 0 available for user.  
5
F0  
F0 is not to be confused with the F0 flag in the CESTATUS register.  
Register bank select control bits. The contents of RS1 and RS0 select the  
working register bank:  
4
RS1  
RS1/RS0  
00  
Bank selected  
Bank 0  
Location  
0x00 – 0x07  
0x08 – 0x0F  
0x10 – 0x17  
0x18 – 0x1F  
01  
Bank 1  
3
RS0  
10  
Bank 2  
11  
Bank 3  
2
1
OV  
Overflow flag.  
User defined flag.  
-
Parity flag, affected by hardware to indicate odd or even number of one bits in  
the Accumulator, i.e. even parity.  
0
P
Stack Pointer (SP, SFR 0x81):  
The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is incremented before  
PUSH and CALL instructions, causing the stack to begin at location 0x08.  
Data Pointer:  
The data pointers (DPTR and DPRT1) are 2 bytes wide. The lower part is DPL(SFR 0x82) and DPL1  
(SFR0x84) and the highest is DPH (SFR0x83) and DPH1 (SFR 0x85). The data pointers can be loaded as  
two registers (e.g. MOV DPL,#data8). They are generally used to access external code or data space  
(e.g. MOVC A,@A+DPTR or MOVX A,@DPTR respectively).  
Program Counter:  
The program counter (PC) is 2 bytes wide and initialized to 0x0000 after reset. The PC is incremented  
when fetching operation code or when operating on data from program memory.  
Port Registers:  
The I/O ports are controlled by Special Function Registers P0, P1 and P2 as shown in Table 12. The contents  
of the SFR can be observed on corresponding pins on the chip. Writing a 1 to any of the ports causes the  
corresponding pin to be at high level (V3P3). Writing a 0 causes the corresponding pin to be held at a low  
level (GND). The data direction registers DIR0, DIR1 and DIR2 define individual pins as input or output  
pins (see Sections 1.5.7 Digital I/O – 71M6531D/F or 1.5.8 Digital I/O – 71M6532D/F).  
v1.3  
© 2005-2010 TERIDIAN Semiconductor Corporation  
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