FDS_6533_6534_004
71M6533/71M6534 Data Sheet
1.4 On-Chip Resources
1.4.1 Oscillator
The 71M6533/71M6534 oscillator drives a standard 32.768 kHz watch crystal. These crystals are accurate
and do not require a high-current oscillator circuit. The oscillator has been designed specifically to handle
these crystals and is compatible with their high impedance and limited power handling capability. The oscil-
lator power dissipation is very low to maximize the lifetime of any battery attached to VBAT.
Oscillator calibration can improve the accuracy of both the RTC and metering. Refer to Section
1.4.3 Real-Time Clock (RTC) for more information.
The oscillator is powered directly and only from VBAT, which therefore must be connected to a DC vol-
tage source. The oscillator requires approximately 100 nA, which is negligible compared to the internal
leakage of a battery.
The oscillator may appear to work when VBAT is not connected, but this mode of operation is not re-
commended.
If VBAT is connected to a drained battery or disconnected, a battery test that sets BME may drain
VBAT’s supply and cause the oscillator to stop. A stopped oscillator may force the device to reset.
Therefore, an unexpected reset during a battery test should be interpreted as a battery failure.
1.4.2 PLL and Internal Clocks
Timing for the device is derived from the 32.768 kHz crystal oscillator output. On-chip timing functions
include:
•
•
•
•
•
The MPU clock (CKMPU)
The emulator clock (2 x CKMPU)
The clock for the CE (CKCE)
The clock driving the delta-sigma ADC along with the FIR (CKADC, CKFIR)
A real time clock (RTC).
The two general-purpose counter/timers contained in the MPU are controlled by CKMPU (see Section
1.3.7 Timers and Counters). Table 37 provides a summary of the clock functions provided.
Table 37: Clock System Summary
MCK Divider / [M40MHZ, M26MHZ]
Brownout Mode
32 kHz
Derived
From
Clock
÷2 / [1,0]
80 MHz
40 MHz
÷3 / [0,1] ÷4** / [0,0]
CKPLL
MCK
Crystal
80 MHz
80 MHz
20 MHz
5 MHz
5 MHz
off
CKPLL
MCK
MCK
MCK
MCK
26.7 MHz
112 kHz
off
CKCE
5 MHz † 10 MHz † 6.6 MHz
CKADC / CKFIR
CKMPU maximum
CK32
5 MHz
10 MHz***
32 kHz
6.6 MHz
28 kHz
28 kHz
6.6 MHz *** 5 MHz ***
32 kHz 32 kHz
** Default state at power-up
*** This is the maximum CKMPU frequency. CKMPU can be reduced from this rate using MPU_DIV.
† CKCE = 10 MHz when CE10MHZ is set, 5 MHz otherwise.
The master clock, MCK, is generated by an on-chip PLL that multiplies the crystal oscillator output fre-
quency (CK32) by 2400 to provide 80 MHz (78.6432 MHz). A divider controlled by the I/O RAM registers
M40MHZ and M26MHZ permits scaling of MCK by ½, ⅓, and ¼. All other clocks are derived from this
scaled MCK output (making them multiples of 32768 Hz), and the clock skew is matched so that the rising
edges of CKADC, CKCE, CK32, and CKMPU are aligned.
v1.1
© 2007-2009 TERIDIAN Semiconductor Corporation
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