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71M6521BE 参数 Datasheet PDF下载

71M6521BE图片预览
型号: 71M6521BE
PDF下载: 下载PDF文件 查看货源
内容描述: 电能计量IC [Energy Meter IC]
分类和应用:
文件页数/大小: 97 页 / 1586 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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71M6521BE  
Energy Meter IC  
DATA SHEET  
JANUARY 2008  
A byte is read by writing the ‘Receive’ command (CMD = 0001) to EECTRL and waiting for the BUSY bit to fall. Upon comple-  
tion, the received data is in EEDATA. The serial transmit and receive clock is 78kHz during each transmission, and the clock is  
held in a high state until the next transmission. The bits in EECTRL are shown in Table 56.  
The EEPROM interface can also be operated by controlling the DIO4 and DIO5 pins directly. However, controlling  
DIO4 and DIO5 directly is discouraged, because it may tie up the MPU to the point where it may become too  
busy to process interrupts.  
Status  
Bit  
Read/  
Write  
Reset  
State  
Name  
Polarity  
Description  
7
6
5
4
ERROR  
BUSY  
R
R
R
R
0
0
1
1
Positive  
Positive  
1 when an illegal command is received.  
1 when serial data bus is busy.  
RX_ACK  
TX_ACK  
Negative 0 indicates that the EEPROM sent an ACK bit.  
Negative 0 indicates when an ACK bit has been sent to the EEPROM  
CMD  
Operation  
0000  
No-op. Applying the no-op command will stop the I2C clock  
(SCK, DIO4). Failure to issue the no-op command will keep  
the SCK signal toggling.  
0010  
0011  
0101  
Receive a byte from EEPROM and send ACK.  
Transmit a byte to EEPROM.  
Positive,  
see CMD  
Table  
3-0  
CMD[3:0]  
W
0000  
Issue a ‘STOP’ sequence.  
0110  
1001  
Receive the last byte from EEPROM and do not send ACK.  
Issue a ‘START’ sequence.  
Others No Operation, set the ERROR bit.  
Table 56: EECTRL Status Bits  
Three-Wire EEPROM Interface  
A 500kHz three-wire interface, using SDATA, SCK, and a DIO pin for CS is available. The interface is selected with  
DIO_EEX=3. The same 2-wire EECTRL register is used, except the bits are reconfigured, as shown in Table 57. When EECTRL  
is written, up to 8 bits from EEDATA are either written to the EEPROM or read from the EEPROM, depending on the values of  
the EECTRL bits.The timing diagrams in Figure 9 through Figure 13 describe the 3-wire EEPROM interface behavior. All  
commands begin when the EECTRL register is written. Transactions start by first raising the DIO pin that is connected to CS.  
Multiple 8-bit or less commands such as those shown in Figure 9 through Figure 13 are then sent via EECTRL and EEDATA.  
When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM will be driving SDATA,  
but will transition to HiZ (high impedance) when CS falls. The firmware should then immediately issue a write command with  
CNT=0 and HiZ=0 to take control of SDATA and force it to a low-Z state.  
Page: 42 of 97  
© 2005-2008 TERIDIAN Semiconductor Corporation  
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