71M6521BE
Energy Meter IC
DATA SHEET
JANUARY 2008
Control
Bit
Name
Read/Write
Description
Wait for Ready. If this bit is set, the trailing edge of BUSY will be delayed
until a rising edge is seen on the data line. This bit can be used during the
last byte of a Write command to cause the INT5 interrupt to occur when the
EEPROM has finished its internal write sequence. This bit is ignored if
HiZ=0.
7
WFR
W
R
Asserted while serial data bus is busy. When the BUSY bit falls, an INT5
interrupt occurs.
6
BUSY
Indicates that the SD signal is to be floated to high impedance immediately
after the last SCK rising edge.
5
4
HiZ
RD
W
W
Indicates that EEDATA is to be filled with data from EEPROM.
Specifies the number of clocks to be issued. Allowed values are 0 through
8. If RD=1, CNT bits of data will be read MSB first, and right justified into
the low order bits of EEDATA. If RD=0, CNT bits will be sent MSB first to
EEPROM, shifted out of EEDATA’s MSB. If CNT is zero, SDATA will
simply obey the HiZ bit.
3-0
CNT[3:0]
W
Table 57: EECTRL bits for 3-wire interface
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- No HiZ
SCLK (output)
D7
D6
D5
D4
D3
D2
SDATA (output)
SDATA output Z
BUSY (bit)
(LoZ)
Figure 9: 3-Wire Interface. Write Command, HiZ=0.
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- With HiZ
SCLK (output)
D7
D6
D5
D4
D3
D2
SDATA (output)
SDATA output Z
BUSY (bit)
(LoZ)
(HiZ)
Figure 10: 3-Wire Interface. Write Command, HiZ=1
V1.0
© 2005-2008 TERIDIAN Semiconductor Corporation
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