71M6521BE
Energy Meter IC
DATA SHEET
JANUARY 2008
The control resources selectable for the DIO pins are listed in Table 55. If more than one input is connected to the same
resource, the resources are combined using a logical OR.
DIO_R Value
Resource Selected for DIO Pin
NONE
0
1
2
3
4
5
6
7
Reserved
T0 (counter0 clock)
T1 (counter1 clock)
High priority I/O interrupt (INT0 rising)
Low priority I/O interrupt (INT1 rising)
High priority I/O interrupt (INT0 falling)
Low priority I/O interrupt (INT1 falling)
Table 55: Selectable Controls using the DIO_DIR Bits
LCD Drivers
The device contains 20 dedicated LCD segment drivers in addition to the 15 multi-use pins described above. Thus, the device
is capable of driving between 80 to 140 pixels of LCD display with 25% duty cycle (or 60 to 105 pixels with 33% duty cycle). At
eight pixels per digit, this corresponds to 10 to 17 digits.
The LCD drivers are grouped into 4 commons and 35 segment drivers. The LCD interface is flexible and can drive either digit
segments or enunciator symbols.
Segment drivers SEG18 and SEG19 can be configured to blink at either 0.5Hz or 1Hz. The blink rate is controlled by LCD_Y.
There can be up to four pixels/segments connected to each of these drivers. LCD_BLKMAP18[3:0] and LCD_BLKMAP19[3:0]
identify which pixels, if any, are to blink.
LCD interface memory is powered by the non-volatile supply. The bits of the LCD memory are preserved in
LCD and SLEEP modes, even if their pin is not configured as SEG. In this case, they can be useful as general-
purpose non-volatile storage.
Battery Monitor
The battery voltage is measured by the ADC during alternative MUX frames if the BME (Battery Measure Enable) bit is set.
While BME is set, an on-chip 45kΩ load resistor is applied to the battery and a scaled fraction of the battery voltage is applied
to the ADC input. After each alternative MUX frame, the result of the ADC conversion is available at CE DRAM address 0x07.
BME is ignored and assumed zero when system power is not available. See the Battery Monitor section of the Electrical
Specification section for details regarding the ADC LSB size and the conversion accuracy.
EEPROM Interface
The 71M6521BE provides hardware support for either type of EEPROM interface, a two-pin interface and a three-pin interface.
The interfaces use the EECTRL and EEDATA registers for communication.
Two-Pin EEPROM Interface
The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is multiplexed onto DIO4
(SCK) and DIO5 (SDA) controlled by the DIO_EEX bit (see I/O RAM Table). The MPU communicates with the interface
through two SFR registers: EEDATA and EECTRL. If the MPU wishes to write a byte of data to EEPROM, it places the data in
EEDATA and then writes the ‘Transmit’ command (CMD = 0011) to EECTRL. The write to EECTRL initiates the transmit
operation. The transmit operation is finished when the BUSY bit falls. INT5 is also asserted when BUSY falls. The MPU can
then check the RX_ACK bit to see if the EEPROM acknowledged the transmission.
V1.0
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