71M6521BE
Energy Meter IC
DATA SHEET
JANUARY 2008
The mass erase sequence is:
1. Write 1 to the FLSH_MEEN bit (SFR address 0xB2[1].
2. Write pattern 0xAA to FLSH_ERASE (SFR address 0x94)
The mass erase cycle can only be initiated when the ICE port is enabled.
The page erase sequence is:
1. Write the page address to FLSH_PGADR (SFR address 0xB7[7:1]
2. Write pattern 0x55 to FLSH_ERASE (SFR address 0x94)
The MPU may write to the flash memory. This is one of the non-volatile storage options available to the user in addition to
external EEPROM.
FLSH_PWE (flash program write enable) differentiates 80515 data store instructions (MOVX@DPTR,A) between Flash and
XRAM writes.
Updating individual bytes in flash memory:
The original state of a flash byte is 0xFF (all ones). Once, a value other than 0xFF is written to a flash memory cell, overwriting
with a different value usually requires that the cell is erased first. Since cells cannot be erased individually, the page has to be
copied to RAM, followed by a page erase. After this, the page can be updated in RAM and then written back to the flash
memory.
MPU RAM: The 71M6521BE includes 2K-bytes of static RAM memory on-chip (XRAM) plus 256-bytes of internal RAM in the
MPU core. The 2K-bytes of static RAM are used for data storage during normal MPU operations.
CE DRAM: The CE DRAM is the working data memory of the CE (128 32-bit words). The MPU can read and write the CE
DRAM as the primary means of data communication between the two processors.
Optical Interface
The device includes an interface to implement an IR/optical port. The pin OPT_Tx is designed to directly drive an external LED
for transmitting data on an optical link. The pin OPT_RX is designed to sense the input from an external photo detector used
as the receiver for the optical link. These two pins are connected to a dedicated UART port (UART1).
The OPT_TX and OPT_RX pins can be inverted with configuration bits OPT_TXINV and OPT_RXINV, respectively.
Additionally, the OPT_TX output may be modulated at 38kHz. Modulation is available when system power is present (i.e. not
in BROWNOUT mode). The OPT_TXMOD bit enables modulation. Duty cycle is controlled by OPT_FDC[1:0], which can select
50%, 25%, 12.5%, and 6.25% duty cycle. 6.25% duty cycle means OPT_TX is low for 6.25% of the period. Figure 7 illustrates
the OPT_TX generator.
When not needed for the optical UART, the OPT_TX pin can alternatively be configured as DIO2 or WPULSE. The
configuration bits are OPT_TXE[1:0]. Likewise, OPT_RX can alternately be configured as DIO_1. Its control is OPT_RXDIS.
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