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71M6513-IGT/F 参数 Datasheet PDF下载

71M6513-IGT/F图片预览
型号: 71M6513-IGT/F
PDF下载: 下载PDF文件 查看货源
内容描述: [Analog Circuit,]
分类和应用:
文件页数/大小: 104 页 / 1320 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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71M6513/71M6513H  
3-Phase Energy Meter IC  
A Maxim Integrated Products Brand  
DATA SHEET  
AUGUST 2011  
Accumulation Interval m+2  
Accumulation Interval m  
Accumulation Interval m+1  
MUX  
MUX  
MUX  
MUX  
MUX  
MUX  
MUX  
cycle 1  
cycle 2 cycle 3  
cycle n  
cycle n  
cycle 1  
cycle 1  
Chop Polarity  
Re-  
versed  
Re-  
versed  
Re-  
Re-  
versed  
Re-  
versed  
Positive  
Positive  
Positive  
Positive  
Positive  
versed  
Positive  
CE_BUSY interrupt  
(falling edge)  
XFER_BUSY interrupt  
(falling edge)  
Figure 21: Chop Polarity w/ Automatic Chopping  
If temperature compensation or accurate reading of the die temperature is required, alternate multiplexer cycles have to be  
inserted in between the regular cycles. This is done under MPU firmware control by asserting the MUX_ALT bit whenever  
necessary. Since die temperature usually changes very slowly, alternate multiplexer cycles have to be inserted very  
infrequently. Usually, an alternate multiplexer cycle is inserted once for every accumulation period, i.e. after each  
XFER_BUSY interrupt. This sequence is shown in Figure 22.  
Accumulation Interval m+2  
Accumulation Interval m  
Accumulation Interval m+1  
MUX  
cycle 2 cycle 3  
MUX  
MUX  
cyclen  
MUX  
cyclen  
alt. MUX  
cycle  
alt. MUX  
cycle  
alt. MUX  
cycle  
Chop Polarity  
Re-  
versed  
Re-  
Re-  
versed  
Re-  
versed  
Re-  
versed  
Positive  
Positive  
Positive  
Positive  
Positive  
Positive  
versed  
CE_BUSY interrupt  
XFER_BUSY interrupt  
MUX_ALT  
Figure 22: Sequence with Alternate Multiplexer Cycles  
This sequence has the disadvantage that the alternate multiplexer cycle is always operated with positive connection.  
Consequently, DC offset will appear on the temperature measurement, which will decrease the accuracy of this measurement  
and thus cause temperature reading and compensation to be less accurate.  
The sequence shown in Figure 23 uses the CHOP_EN bits to control the chopper polarity after each XFER_BUSY interrupt.  
CHOP_EN is controlled to alternate between 10 (positive) and 01 (reversed) for the first multiplexer cycle following each  
Page: 56 of 104  
© 2005-2011 Teridian Semiconductor Corporation