71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
AUGUST 2011
Power-Up: After power-up, the 71M6513/6513H is in reset as long as V1 < VBIAS. As soon as V1 exceeds VBIAS, the reset
timer is started which takes the MPU out of reset after 4100 oscillator cycles (see Figure 20). The MPU then initiates its pre-
boot phase lasting 32 cycles. The supply current will be low but not zero during power-up. It will increase, once V1 exceeds
VBIAS and will increase to the nominal value once the preboot phase starts. The supply current may then be reduced under
firmware control, following the steps specified in Battery Operation and Power Save Modes.
V3P3
3.3V
V2P5
1.5V
0V
V1
POWER
DOWN
PRE-
BOOT
PWR
UP
RESET TIMER
FIRMWARE HAS CONTROL OVER CHIP...
V1 > VBIAS
SUPPLY CURRENT
nominal
0mA
1ms
125ms
Figure 20: Timing Diagram for Voltages, Current and Operation Modes after Power-Up
Battery Operation
When V1 is lower than VBIAS, the external battery will power the following parts of the 71M6513/6513H:
•
•
RTC
Crystal oscillator circuitry
•
•
MPU XRAM
WD_OVF bit
Power Save Modes
In normal mode of operation, running on 3.3V supply, various resources of the 71M6513/6513H may be shut down by the
MPU firmware in order to reduce power consumption while other essential resources such as UARTs may remain active.
Table 59 outlines these resources and their typical current consumption (based on initial condition MPU_DIV = 0).
Typical
Savings
Power Saving Measure
Software Control
Disable the CE
CE_EN = 0
ADC_DIS = 1
CKOUTDIS = 1
ECK_DIS = 1 *)
FLASH66Z =1
LCD_BSTEN = 0
RTM_EN = 0
0.16mA
1.8mA
Disable the ADC
Disable clock test output CKTEST
Disable emulator clock
0.6mA
0.1mA
Set flash read pulse timing to 33 ns
Disable the LCD voltage boost circuitry
Disable RTM outputs
0.04mA
0.9mA
0.01mA
0.4mA/MHz
Increase the clock divider for the MPU
MPU_DIV = X
*) This bit is to be used with caution! Inadvertently setting this bit will inhibit access to the part with the ICE interface and thus
preclude flash erase and programming operations.
Table 59: Power Saving Measures
Page: 54 of 104
© 2005-2011 Teridian Semiconductor Corporation
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
