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71M6513-IGT/F 参数 Datasheet PDF下载

71M6513-IGT/F图片预览
型号: 71M6513-IGT/F
PDF下载: 下载PDF文件 查看货源
内容描述: [Analog Circuit,]
分类和应用:
文件页数/大小: 104 页 / 1320 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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71M6513/71M6513H  
3-Phase Energy Meter IC  
A Maxim Integrated Products Brand  
DATA SHEET  
AUGUST 2011  
Data Flow  
The data flow between CE and MPU is shown in Figure 17. In a typical application, the 32-bit compute engine (CE)  
sequentially processes the samples from the voltage inputs on pins IA, VA, IB, VB, IC, and VC performing calculations to  
measure active power (Wh), reactive power (VARh), A2h, and V2h for four-quadrant metering. These measurements are then  
accessed by the MPU, processed further and output using the peripheral devices available to the MPU.  
Pulses  
IRQ  
Processed  
Metering  
Data  
CE  
MPU  
Samples  
Data  
Pre-  
Processor  
Post-  
Processor  
I/O RAM (Configuration RAM)  
Figure 17: MPU/CE Data Flow  
CE/MPU Communication  
Figure 18 shows the functional relationship between CE and MPU. The CE is controlled by the MPU via shared registers in the  
I/O RAM and by registers in the CE DRAM. The CE outputs two interrupt signals to the MPU: CE_BUSY and XFER_BUSY,  
which are connected to the MPU interrupt service inputs as external interrupts. CE_BUSY indicates that the CE is actively  
processing data. This signal will occur once every multiplexer cycle. XFER_BUSY indicates that the CE is updating data to the  
output region of the CE RAM. This will occur whenever the CE has finished generating a sum by completing an accumulation  
interval determined by SUM_CYCLES * PRE_SAMPS samples. Interrupts to the MPU occur on the falling edges of the  
XFER_BUSY and CE_BUSY signals.  
Figure 19 shows the sequence of events between CE and MPU upon reset or power-up. In a typical application, the sequence  
of events is as follows:  
1) Upon power-up, the MPU initializes the hardware, including disabling the CE  
2) The MPU loads the code for the CE into the CE PRAM  
3) The MPU loads CE data into the CE DRAM.  
4) The MPU starts the CE by setting the CE_EN bit in the I/O RAM.  
5) The CE then repetitively executes its code, generating results and storing them in the CE DRAM  
It is important to note that the length of the accumulation interval, as determined by NACC, the product of SUM_CYCLES and  
PRE_SAMPS is not an exact multiple of 1000ms. For example, if SUM_CYCLES = 60, and PRE_SAMPS = 00 (42), the resulting  
accumulation interval is:  
NACC  
fS  
6042  
32768Hz  
13  
2520  
τ =  
=
=
= 999.75ms  
2520.62Hz  
This means that accurate time measurements require the RTC.  
Page: 52 of 104  
© 2005-2011 Teridian Semiconductor Corporation