71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
AUGUST 2007
SSI_BEG[7:0]
SSI_END[7:0]
2071[7:0]
2072[7:0]
R/W The beginning and ending address of the transfer region of the CE
data memory. If the SSI is enabled, a block of words starting with
SSI_BEG and ending with SSI_END will be sent. SSI_END must be
larger than SSI_BEG. The maximum number of output words is limited
by the number of SSI clocks in a CE code pass—see FIR_LEN,
MUX_DIV, and SSI_10M.
Together w/ PRE_SAMPS, this value determines (for the CE) the
SUM_CYCLES
[5:0]
2001[5:0]
2000[3:0]
R/W
number of samples in one sum cycle between XFER interrupts.
Number of samples = PRE_SAMPS*SUM_CYCLES.
TMUX[3:0]
R/W Selects one of 16 inputs for TMUXOUT.
0 – DGND (analog)
1 – IBIAS (analog)
2 – PLL_2.5V (analog)
3 – VBIAS (analog)
4 – RTM (Real time output from CE)
5 – WDTR_EN (Comparator 1 Output AND V1LT3)
6 – reserved
7 – reserved
8 – RXD (from Optical interface)
9 – MUX_SYNC (from MUX_CTRL)
A – CK_10M
B – CK_MPU
C – reserved for production test
D – RTCLK
E – CE_BUSY
F – XFER_BUSY
RESERVED
TRIMSEL
2005[7]
20FD
R/W Must be zero.
W
Selects the temperature trim fuse to be read with the TRIM register
(TRIMM[2:0]: 4, TRIMBGA: 5, TRIMBGB: 6)
TRIM
20FF
R
Contains TRIMBGA, TRIMBGB, or TRIMM[2:0] depending on the
value written to TRIMSEL. If TRIMBGB = 0 then the IC is a 6511 else
the IC is a 6511H.
VERSION[7:0]
VREF_CAL
2006
R
The silicon revision number. This data sheet does not apply to
revisions < 000 0100.
2004[7]
R/W Brings VREF out to the VREF pin. This feature is disabled when
VREF_DIS=1.
VREF_DIS
WD_RST
2004[3]
SFR E8[7]
R/W Disables the internal voltage reference.
W
Resets the WD timer. The WDT is reset when a 1 is written to this bit.
Only byte operations on the whole WDI register should be used.
WD_OVF
2002[2]
R/W The WD overflow status bit. This bit is set when the WD timer
overflows. It is powered by the VBAT pin and at boot-up will indicate if
the part is recovering from a WD overflow or a power fault. This bit
should be cleared by the MPU on boot-up. It is also automatically
cleared when RESETZ is low.
Page: 63 of 95
© 2005-2007 TERIDIAN Semiconductor Corporation
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